A Coupling-based Complexity Metric for Remote Component-based Software Systems Toward Maintainability Estimation. - Hironori Washizaki; Tomoki Nakagawa; Yuhki Saito; Yoshiaki Fukazawa (APSEC, 2006)

A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. - Shintaro Izumi; Ken Yamashita; Masanao Nakano; Tomoki Nakagawa; Yuki Kitahara; Koji Yanagida; Shusuke Yoshimoto; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; et al. (BioCAS, 2014)

A 6T-4C shadow memory using plate line and word line boosting. - Tomoki Nakagawa; Shintaro Izumi; Shusuke Yoshimoto; Koji Yanagida; Yuki Kitahara; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISCAS, 2014)

A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Koji Nii; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (CICC, 2015)

A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. - Tomoki Nakagawa; Shintaro Izumi; Koji Yanagida; Yuki Kitahara; Shusuke Yoshimoto; Yohei Umeki; Haruki Mori; Hiroto Kitahara; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; et al. (ISCAS, 2015)

Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. - Shintaro Izumi; Ken Yamashita; Masanao Nakano; Shusuke Yoshimoto; Tomoki Nakagawa; Yozaburo Nakai; Hiroshi Kawaguchi 001; Hiromitsu Kimura; Kyoji Marumoto; Takaaki Fuchikami; Yoshikazu Fujimori; Hiroshi Nakajima; et al. (IEEE Trans. Biomed. Circuits Syst., 2015)

An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ICECS, 2016)

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Kazushige Kanda; Takahiro Shimizu; Jun Nakai; Osamu Nagao; Naoki Kobayashi 004; Makoto Miakashi; Yasushi Nagadomi; Takeshi Nakano; Takahisa Kawabe; Taira Shibuya; Mario Sako; et al. (ISSCC, 2019)

A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. - Haruki Mori; Tomoki Nakagawa; Yuki Kitahara; Yuta Kawamoto; Kenta Takagi; Shusuke Yoshimoto; Shintaro Izumi; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Takahisa Kawabe; Taira Shibuya; Mario Sako; Kosuke Yanagidaira; Toshifumi Hashimoto; Hiroki Date; Manabu Sato; Tomoki Nakagawa; Junji Musha; Takatoshi Minamoto; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 2020)

Sonic communication using multiple bands with electrostatic drivers. - Tomoki Nakagawa; Toshio Fukuda (SII, 2022)