An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. - Takeshi Sakata; Masashi Horiguchi; Tomonori Sekiguchi; Shigeki Ueda; Hitoshi Tanaka; Eiji Yamasaki; Yoshinobu Nakagome; Masakazu Aoki; Toru Kaga; Makoto Ohkura; Ryo Nagai; Fumio Murai; et al. (IEEE J. Solid State Circuits, 1995)

Low-noise, high-speed data transmission using a ringing-canceling output buffer. - Tomonori Sekiguchi; Masashi Horiguchi; Takeshi Sakata; Yoshinobu Nakagome; Shigeki Ueda; Masakazu Aoki (IEEE J. Solid State Circuits, 1995)

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. - Hiroki Fujisawa; Takeshi Sakata; Tomonori Sekiguchi; Osamu Nagashima; Katsutaka Kimura; Kazuhiko Kajigaya (IEEE J. Solid State Circuits, 1997)

A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. - Tsugio Takahashi; Tomonori Sekiguchi; Riichiro Takemura; Seiji Narui; Hiroki Fujisawa; Shinichi Miyatake; Makoto Morino; Koji Arai; Satoru Yamada; Shoji Shukuri; Masayuki Nakamura; Yoshitaka Tadaki; et al. (IEEE J. Solid State Circuits, 2001)

A low-impedance open-bitline array for multigigabit DRAM. - Tomonori Sekiguchi; Kiyoo Itoh 001; Tsugio Takahashi; Masahiro Sugaya; Hiroki Fujisawa; Masayuki Nakamura; Kazuhiko Kajigaya; Katsutaka Kimura (IEEE J. Solid State Circuits, 2002)

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. - Satoru Hanzawa; Takeshi Sakata; Kazuhiko Kajigaya; Riichiro Takemura; Tomonori Sekiguchi; Takayuki Kawahara (ICC, 2005)

A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi (ISLPED, 2006)

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. - Satoru Akiyama; Tomonori Sekiguchi; Kazuhiko Kajigaya; Satoru Hanzawa; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi; Satoru Akiyama; Satoru Hanzawa; Kazuhiko Kajigaya; Takayuki Kawahara (IEICE Trans. Electron., 2007)

Memory at VLSI Circuits Symposium. - Kiyoo Itoh 001; Hideaki Kurata; Kenichi Osada; Tomonori Sekiguchi (IEEE J. Solid State Circuits, 2008)

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. - Satoru Akiyama; Tomonori Sekiguchi; Riichiro Takemura; Akira Kotabe; Kiyoo Itoh 001 (ISSCC, 2009)

0.5-V Low- V T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays. - Akira Kotabe; Yoshimitsu Yanagawa; Satoru Akiyama; Tomonori Sekiguchi (IEEE J. Solid State Circuits, 2010)

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. - Tomonori Sekiguchi; Kazuo Ono; Akira Kotabe; Yoshimitsu Yanagawa (IEEE J. Solid State Circuits, 2011)

A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. - Satoru Akiyama; Riichiro Takemura; Tomonori Sekiguchi; Akira Kotabe; Kiyoo Itoh 001 (IEICE Trans. Electron., 2012)

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. - Akira Kotabe; Riichiro Takemura; Yoshimitsu Yanagawa; Tomonori Sekiguchi; Kiyoo Itoh 001 (IEICE Trans. Electron., 2012)

A concentrated springs architecture for single-digit frequency symmetry in Si MEMS gyroscope. - Joan Giner; Yuhua Zhang; Takashi Shiota; Daisuke Maeda; Kazuo Ono; Shinya Kajiyama; Takashi Oshima; Taizo Yamawaki; Tomonori Sekiguchi (IEEE SENSORS, 2016)

A low 1/f-noise accelerometer frontend using chopper stabilization at a frequency matched with a notch of quantization noise. - Kazuo Ono; Daisuke Maeda; Takashi Oshima; Toshiaki Nakamura; Joan Giner; Tomonori Sekiguchi (IEEE SENSORS, 2016)

Design of Perforated Membrane for Low-Noise Capacitive MEMS Accelerometers. - Atsushi Isobe; Yudai Kamada; Takashi Oshima; Yuki Furubayashi; Noriyuki Sakuma; Chisaki Takubo; Yasushi Tainaka; Keiki Watanabe; Tomonori Sekiguchi (IEEE SENSORS, 2018)

A 22ng/√Hz 17mW MEMS Accelerometer with Digital Noise-Reduction Techniques. - Yuki Furubayashi; Takashi Oshima; Taizo Yamawaki; Keiki Watanabe; Keijiro Mori; Naoki Mori; Akira Matsumoto; Hideto Kazama; Yudai Kamada; Atsushi Isobe; Tomonori Sekiguchi (ISSCC, 2019)

A 22-ng/ $ surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques. - Yuki Furubayashi; Takashi Oshima; Taizo Yamawaki; Keiki Watanabe; Keijiro Mori; Naoki Mori; Akira Matsumoto; Yudai Kamada; Atsushi Isobe; Tomonori Sekiguchi (IEEE J. Solid State Circuits, 2020)

Generating Shuttling Procedures for Constrained Silicon Quantum Dot Array. - Naoto Sato; Tomonori Sekiguchi; Takeru Utsugi; Hiroyuki Mizuno (CoRR, 2024)