Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits. - Tomoya Kitai; Tomohiro Yoneda (PRDC, 2001)

Automatic Derivation of Timing Constraints by Failure Analysis. - Tomohiro Yoneda; Tomoya Kitai; Chris J. Myers (CAV, 2002)

Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. - Tomoya Kitai; Yusuke Oguro; Tomohiro Yoneda; Eric Mercer; Chris J. Myers (PRDC, 2002)

Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. - Tomoya Kitai; Tomohiro Yoneda; Chris J. Myers (IEICE Trans. Inf. Syst., 2005)