Development of Pipeline Time Chart Too for Microprocessor Design Education. - Tomoyuki Morimoto; Toshiyuki Tsutsumi (ICCE, 2010)

Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applications. - Yukoh Matsumoto; Tomoyuki Morimoto; Michiya Hagimoto; Hiroyuki Uchida; Nobuyuki Hikichi; Fumito Imura; Hiroshi Nakagawa; Masahiro Aoyagi (COOL Chips, 2012)

Early Development of Visualization Tool for Instruction Implement of Microprocessor. - Tomoyuki Morimoto; Ryouhei Iwamoto; Toshiyuki Tsutsumi (ISCIT, 2019)

Visualization Tool of Microprocessor Instruction for Designing New Architecture with Meta-Instructions. - Tomoyuki Morimoto; Shunsuke Onogi; Tadahiro Ogita; Ryota Kawamata; Ziming Wang; Toshiyuki Tsutsumi (ISCIT, 2022)

Initial Implementation and Utilization of Instruction Dynamic Simulation in MEIMAT. - Tadahiro Ogita; Tomoyuki Morimoto; Shunsuke Onogi; Ryota Kawamata; Ziming Wang; Toshiyuki Tsutsumi (ISCIT, 2022)

Microprocessor Instruction Design Tool for RISC-V Architecture. - Jiahui Luo; Tomoyuki Morimoto; Tadahiro Ogita; Ryota Kawamata; Zi-Ming Wang; Toshiyuki Tsutsumi (ISCIT, 2023)

Visualization and Simulation of Any MPU Architecture Design with Meta-Instruction. - Tomoyuki Morimoto; Ziming Wang; Jiahui Luo; Sota Ogawa; Toshiyuki Tsutsumi (ISCIT, 2024)