Design and evaluation of variable stages pipeline processor chip. - Tomoyuki Nakabayashi; Takahiro Sasaki; Kazuhiko Ohno; Toshio Kondo (ASP-DAC, 2011)

Low power semi-static TSPC D-FFs using split-output latch. - Tomoyuki Nakabayashi; Takahiro Sasaki; Kazuhiko Ohno; Toshio Kondo (ISOCC, 2011)

Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture. - Tomoyuki Nakabayashi; Takahiro Sasaki; Kazuhiko Ohno; Toshio Kondo (ICNC, 2012)

Design and evaluation of variable stages pipeline processor with low-energy techniques. - Tomoyuki Nakabayashi; Takahiro Sasaki; I. K. Ohno; Toshio Kondo (IET Comput. Digit. Tech., 2012)

Dynamic BTB Resizing for Variable Stages Superscalar Architecture. - Tomoyuki Nakabayashi; Takahiro Sasaki; Toshio Kondo (CANDAR, 2013)

FabCache: Cache Design Automation for Heterogeneous Multi-core Processors. - Takaki Okamoto; Tomoyuki Nakabayashi; Takahiro Sasaki; Toshio Kondo (CANDAR, 2013)

Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor. - Takahiro Sasaki; Tomoyuki Nakabayashi; Kazumasa Nomura; Kazuhiko Ohno; Toshio Kondo (IET Comput. Digit. Tech., 2013)

Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip. - Tomoyuki Nakabayashi; Takahiro Sasaki; Hitoshi Nakamura; Kazuhiko Ohno; Toshio Kondo (Int. J. Netw. Comput., 2013)

Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. - Tomoyuki Nakabayashi; Tomoyuki Sugiyama; Takahiro Sasaki; Eric Rotenberg; Toshio Kondo (ASP-DAC, 2014)

Detail Design and Evaluation of Fab Cache. - Takaki Okamoto; Tomoyuki Nakabayashi; Takahiro Sasaki; Toshio Kondo (CANDAR, 2014)