Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. - Tomoyuki Yoda; Atsushi Takahashi 001; Yoji Kajitani (ASP-DAC, 1999)

Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems. - Takeshi Kitahara; Hiroyuki Hara; Shinichiro Shiratake; Yoshiki Tsukiboshi; Tomoyuki Yoda; Tetsuaki Utsumi; Fumihiro Minami (ASP-DAC, 2006)