Application-dependent scaling tradeoffs and optimization in the SoC era. - Carlos H. Diaz; Mi-Chang Chang; Tong-Chern Ong; Jack Yuan-Chen Sun (CICC, 2002)

The embedded SCR NMOS and low capacitance ESD protection device. - Jian-Hsing Lee; Yi-Hsun Wu; K. R. Peng; R. Y. Chang; Talee Yu; Tong-Chern Ong (CICC, 2002)

Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era. - Carlos H. Diaz; Mi-Chang Chang; Tong-Chern Ong; Jack Yuan-Chen Sun (IEEE J. Solid State Circuits, 2003)

A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O. - Jian-Hsing Lee; Jiaw-Ren Shih; Yi-Hsun Wu; Kuo-Feng Yu; Tong-Chern Ong (ISCAS (2), 2005)

Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. - Hung-Chang Yu; Kai-Chun Lin; Ku-Feng Lin; Chin-Yi Huang; Yu-Der Chih; Tong-Chern Ong; Tsung-Yung Jonathan Chang; Sreedhar Natarajan; Luan C. Tran (ISSCC, 2013)

Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window. - Chien-An Lai; Chung-Cheng Chou; Chi-Hsiang Weng; Zheng-Jun Lin; Pei-Ling Tseng; Chien-Fan Wang; Chih-Chen Wang; Chin-I Su; Wei-Chi Chen; Yu-Cheng Lin; Tong-Chern Ong; Chi Chang; et al. (A-SSCC, 2018)

A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range. - Chung-Cheng Chou; Zheng-Jun Lin; Chien-An Lai; Chin-I Su; Pei-Ling Tseng; Wei-Chi Chen; Wu-Chin Tsai; Wen-Ting Chu; Tong-Chern Ong; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2020)