A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. - Tong Jing; Xianlong Hong; Haiyun Bao; Yici Cai; Jingyu Xu 001; Jun Gu (ISCAS (1), 2002)

UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. - Tong Jing; Xianlong Hong; Haiyun Bao; Yici Cai; Jingyu Xu 001; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2003)

A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Yici Cai; Jun Gu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

An efficient hierarchical timing-driven Steiner tree algorithm for global routing. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Yici Cai; Jun Gu (Integr., 2003)

CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing. - Xianlong Hong; Tong Jing; Jingyu Xu 001; Haiyun Bao; Jun Gu (J. Comput. Sci. Technol., 2003)

SSTT: Efficient Local Search for GSI Global Routing. - Tong Jing; Xianlong Hong; Haiyun Bao; Jingyu Xu 001; Jun Gu (J. Comput. Sci. Technol., 2003)

Efficient octilinear Steiner tree construction based on spanning graphs. - Qi Zhu 002; Hai Zhou 001; Tong Jing; Xianlong Hong; Yang Yang 040 (ASP-DAC, 2004)

Performance and RLC crosstalk driven global routing. - Ling Zhang; Tong Jing; Xianlong Hong; Jingyu Xu 001; Jinjun Xiong; Lei He 001 (ISCAS (5), 2004)

An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. - Yin Wang; Xianlong Hong; Tong Jing; Yang Yang 040; Xiaodong Hu 001; Guiying Yan (PATMOS, 2004)

UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. - Tong Jing; Xianlong Hong; Jingyu Xu 001; Haiyun Bao; Chung-Kuan Cheng; Jun Gu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. - Yang Yang 040; Tong Jing; Xianlong Hong; Yu Hu 002; Qi Zhu 002; Xiaodong Hu 001; Guiying Yan (ASAP, 2005)

An-OARSMan: obstacle-avoiding routing tree construction with good length performance. - Yu Hu 002; Tong Jing; Xianlong Hong; Zhe Feng 002; Xiaodong Hu 001; Guiying Yan (ASP-DAC, 2005)

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. - Tong Jing; Ling Zhang; Jinghong Liang; Jingyu Xu 001; Xianlong Hong; Jinjun Xiong; Lei He 001 (ASP-DAC, 2005)

The polygonal contraction heuristic for rectilinear Steiner tree construction. - Yin Wang; Xianlong Hong; Tong Jing; Yang Yang 040; Xiaodong Hu 001; Guiying Yan (ASP-DAC, 2005)

Rotational Steiner Ratio Problem Under Uniform Orientation Metrics. - Songpu Shang; Xiaodong Hu 001; Tong Jing (CJCDGCGT, 2005)

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Yang Yang 040 (ISQED, 2005)

A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. - Yu Hu 002; Tong Jing; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (SAMOS, 2005)

Timing-Driven Global Routing with Efficient Buffer Insertion. - Jingyu Xu 001; Xianlong Hong; Tong Jing (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Spanning graph-based nonrectilinear steiner tree algorithms. - Qi Zhu 002; Hai Zhou 001; Tong Jing; Xianlong Hong; Yang Yang 040 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

DraXRouter: global routing in X-Architecture with dynamic resource assignment. - Zhen Cao; Tong Jing; Yu Hu 002; Yiyu Shi 001; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (ASP-DAC, 2006)

CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. - Yiyu Shi 001; Tong Jing; Lei He 001; Zhe Feng 002; Xianlong Hong (ASP-DAC, 2006)

Average lengths of wire routing under M-architecture and X-architecture. - S. P. Shang; Xiaodong Hu 001; Tong Jing (ISCAS, 2006)

An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. - Zhe Feng 002; Yu Hu 002; Tong Jing; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (ISPD, 2006)

A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Ling Zhang; Jun Gu (Integr., 2006)

ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. - Yu Hu 002; Tong Jing; Zhe Feng 002; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (J. Comput. Sci. Technol., 2006)

Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design. - Jingyu Xu 001; Xianlong Hong; Tong Jing; Yang Yang 040 (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. - Zhen Cao; Tong Jing; Jinjun Xiong; Yu Hu 002; Lei He 001; Xianlong Hong (ASP-DAC, 2007)

Temperature aware microprocessor floorplanning considering application dependent power load. - Chunta Chu; Xinyi Zhang; Lei He 001; Tong Jing (ICCAD, 2007)

Fast dual-vdd buffering based on interconnect prediction and sampling. - Yu Hu 002; King Ho Tam; Tong Jing; Lei He 001 (SLIP, 2007)

Fashion: A Fast and Accurate Solution to Global Routing Problem. - Zhen Cao; Tong Jing; Jinjun Xiong; Yu Hu 002; Zhe Feng 002; Lei He 001; Xianlong Hong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

PQISEM: BN's structure learning based on partial qualitative influences and SEM algorithm from missing data. - Yali Lv; Jian'ai Wu; Tong Jing (Int. J. Wirel. Mob. Comput., 2018)

Cramér-Rao Lower Bound Analysis for Stochastic Model Based Target Parameter Estimation in Multistatic Passive Radar With Direct-Path Interference. - Tong Jing; Gaoming Huang; Wei Tian 004; Huafu Peng (IEEE Access, 2019)