Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic. - Tong Lin 001; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph Sylvester Chang (ISCAS, 2009)

A comparative study on asynchronous Quasi-Delay-Insensitive templates. - Kok-Leong Chang; Tong Lin 001; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. - Weng-Geng Ho; Kwen-Siong Chong; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2012)

A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic. - Kok-Leong Chang; Tong Lin 001; Weng-Geng Ho; Kwen-Siong Chong; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2013)

An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks. - Tong Lin 001; Kwen-Siong Chong; Joseph S. Chang; Bah-Hwee Gwee (IEEE J. Solid State Circuits, 2013)

Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process. - Joseph S. Chang; Kwen-Siong Chong; Wei Shu; Tong Lin 001; Jize Jiang; Ne Kyaw Zwa Lwin; Yang Kang (MWSCAS, 2014)

Fully-Additive printed electronics on flexible substrates: A Fully-Additive RFID tag. - Tong Ge; Joseph S. Chang; Tong Lin 001; Lei Zhang; Lim Geok Soon (MWSCAS, 2014)

A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling pipeline. - Rong Zhou; Kwen-Siong Chong; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (ISCAS, 2015)

Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process. - Jize Jiang; Wei Shu; Kwen-Siong Chong; Tong Lin 001; Ne Kyaw Zwa Lwin; Joseph Sylvester Chang; Jingyuan Liu (ISCAS, 2016)

Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process. - Tong Lin 001; Kwen-Siong Chong; Wei Shu; Ne Kyaw Zwa Lwin; Jize Jiang; Joseph S. Chang (ISCAS, 2016)

Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. - Kwen-Siong Chong; Weng-Geng Ho; Tong Lin 001; Bah-Hwee Gwee; Joseph S. Chang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Deep Learning for Automatic IC Image Analysis. - Xuenong Hong; Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee (DSP, 2018)

Single-Event-Transient Resilient Memory for DSP in Space Applications. - Ne Kyaw Zwa Lwin; H. Sivaramakrishnan; Kwen-Siong Chong; Tong Lin 001; Wei Shu; Joseph S. Chang (DSP, 2018)

Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images. - Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee; Kar-Ann Toh (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Global Template Projection and Matching Method for Training-Free Analysis of Delayered IC Images. - Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee; Kar-Ann Toh (ISCAS, 2019)

A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images. - Deruo Cheng; Yiqiong Shi; Bah-Hwee Gwee; Kar-Ann Toh; Tong Lin 001 (IEEE Intell. Syst., 2019)

Joint Anomaly Detection and Inpainting for Microscopy Images Via Deep Self-Supervised Learning. - Ling Huang; Deruo Cheng; Xulei Yang; Tong Lin 001; Yiqiong Shi; Kaiyi Yang; Bah-Hwee Gwee; Bihan Wen (ICIP, 2021)

Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis. - Yee-Yang Tee; Deruo Cheng; Chye-Soon Chee; Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (CoRR, 2022)

Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision. - Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee; Kar-Ann Toh (IET Circuits Devices Syst., 2022)

GRACER: Graph-Based Standard Cell Recognition in IC Images for Hardware Assurance. - Erdong Huang; Xuenong Hong; Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (IECON, 2023)

SEM2GDS: A Deep-Learning Based Framework To Detect Malicious Modifications In IC Layout. - Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (ISCAS, 2023)

Patch-Based Adversarial Training for Error-Aware Circuit Annotation of Delayered IC Images. - Yee-Yang Tee; Xuenong Hong; Deruo Cheng; Chye-Soon Chee; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning. - Xuenong Hong; Tong Lin 001; Yiqiong Shi; Bah-Hwee Gwee (IEEE Trans. Artif. Intell., 2023)

MLConnect: A Machine Learning Based Connection Prediction Framework for Error Correction in Recovered Circuit. - Xuenong Hong; Zilong Hu; Han Zhang; Yee-Yang Tee; Tong Lin 001; Yiqiong Shi; Deruo Cheng; Bah-Hwee Gwee (ISCAS, 2024)

Integrated Circuit Mask-Generative Adversarial Network for Circuit Annotation With Targeted Data Augmentation. - Yee-Yang Tee; Deruo Cheng; Yiqiong Shi; Tong Lin 001; Bah-Hwee Gwee (IEEE Intell. Syst., 2024)

Multiple Hypothesis Testing for SEM Image Processing: A Case Study on Standard Cell Partition. - Xiaoyu Ma; Yizhen Li; Feng Ji; Tong Lin 001; Yiqiong Shi; Deruo Cheng; Bah-Hwee Gwee (ISCAS, 2025)

SSRNet: Few-shot IC Segmentation in Automated PCB Image Processing. - Yuhang Wang; Xinrui Wang 004; Deruo Cheng; Tong Lin 001; Feng Ji; Yiqiong Shi; Bah-Hwee Gwee (ISCAS, 2025)

Long-Short-GNN: A Novel Graph Neural Network for Detecting FPGA IP Circuits for Hardware Assurance. - Heyi Zhang; Tong Lin 001; Feng Ji; Deruo Cheng; Yiqiong Shi; Bah-Hwee Gwee (ISCAS, 2025)

GNNReveal: A Novel Graph-Neural-Network-Based Attack Method for Integrated Circuit Logic Gate Decamouflaging. - Xuenong Hong; Yee-Yang Tee; Zilong Hu; Tong Lin 001; Yiqiong Shi; Deruo Cheng; Bah-Hwee Gwee (IEEE Intell. Syst., 2025)