Antoni Roca

According to our database, Antoni Roca authored at least 24 papers between 2010 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Voltage Noise Analysis with Ring Oscillator Clocks.

Lucas Machado, Antoni Roca Perez, Jordi Cortadella

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis.

Sergi Alcaide, Carles Hernández, Antoni Roca, Jaume Abella

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Improving performance guarantees in wormhole mesh NoC designs.

Milos Panic, Carles Hernández, Jaume Abella, Antoni Roca, Eduardo Quiñones, Francisco J. Cazorla

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Ring Oscillator Clocks and Margins.

Jordi Cortadella, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar

Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems.

Antoni Roca, Carles Hernández, Mario Lodde, José Flich

Comput. Electr. Eng., 2015

Reactive clocks with variability-tracking jitter.

Jordi Cortadella, Luciano Lavagno, Pedro Lopez, Marc Lupon, Alberto Moreno, Antoni Roca, Sachin S. Sapatnekar

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead.

José Cano, José Flich, Antoni Roca, José Duato, Marcello Coppola, Riccardo Locatelli

IEEE Trans. Computers, 2014

A hierarchical approach for generating regular floorplans.

Javier de San Pedro, Jordi Cortadella, Antoni Roca

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

Silicon-aware distributed switch architecture for on-chip networks.

Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato

J. Syst. Archit., 2013

Built-in fast gather control network for efficient support of coherence protocols.

Mario Lodde, Antoni Roca, José Flich

IET Comput. Digit. Tech., 2013

2012

On the Impact of Within-Die Process Variation in GALS-Based NoC Performance.

Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Enabling High-Performance Crossbars through a Floorplan-Aware Design.

Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato

Proceedings of the 41st International Conference on Parallel Processing, 2012

Heterogeneous network design for effective support of invalidation-based coherency protocols.

Mario Lodde, Toni Roca, José Flich

Proceedings of the 2012 Interconnection Network Architecture, 2012

DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS.

Antoni Roca, José Flich, Giorgos Dimitrakopoulos

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems.

Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A low-latency modular switch for CMP systems.

Antoni Roca, José Flich, Federico Silla, José Duato

Microprocess. Microsystems, 2011

Characterizing the impact of process variation on 45 nm NoC-based CMPs.

Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato

J. Parallel Distributed Comput., 2011

Fault-Tolerant Vertical Link Design for Effective 3D Stacking.

Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato

IEEE Comput. Archit. Lett., 2011

A Distributed Switch Architecture for On-Chip Networks.

Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato

Proceedings of the International Conference on Parallel Processing, 2011

PC-Mesh: A Dynamic Parallel Concentrated Mesh.

Jesús Camacho Villanueva, José Flich, Antoni Roca, José Duato

Proceedings of the International Conference on Parallel Processing, 2011

2010

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.

Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato

Proceedings of the NOCS 2010, 2010

Improving the Performance of GALS-Based NoCs in the Presence of Process Variation.

Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato

Proceedings of the NOCS 2010, 2010

VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks.

Antoni Roca, José Flich, Federico Silla, José Duato

Proceedings of the 2010 International Conference on High Performance Computing, 2010

A Latency-Efficient Router Architecture for CMP Systems.

Antoni Roca, José Flich, Federico Silla, José Duato

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010