A solitary protection measure against scan chain, fault injection, and power analysis attacks on AES. - Tonmoy Dhar; Swarup Bhunia; Amit Ranjan Trivedi (MWSCAS, 2017)

Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation. - Tonmoy Dhar; Sachin S. Sapatnekar (IRPS, 2019)

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2020)

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ICCAD, 2020)

A general approach for identifying hierarchical symmetry constraints for analog circuit layout. - Kishor Kunal; Jitesh Poojary; Tonmoy Dhar; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (ICCAD, 2020)

Learning from Experience: Applying ML to Analog Circuit Design. - Kishor Kunal; Tonmoy Dhar; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Sachin S. Sapatnekar (ISPD, 2020)

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. - Tonmoy Dhar; Jitesh Poojary; Yaguang Li; Kishor Kunal; Meghna Madhusudan; Arvind K. Sharma; Susmita Dey Manasi; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (ASP-DAC, 2021)

Aging of Current DACs and its Impact in Equalizer Circuits. - Tonmoy Dhar; Jitesh Poojary; Ramesh Harjani; Sachin S. Sapatnekar (IRPS, 2021)

Machine Learning Techniques in Analog Layout Automation. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ISPD, 2021)

ALIGN: A System for Automating Analog Layout. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Parijat Mukherjee; et al. (IEEE Des. Test, 2021)

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. - Tonmoy Dhar; Ramprasath S 001; Jitesh Poojary; Soner Yaldiz; Steven M. Burns; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2022)

GNN-Based Hierarchical Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)