HTOL SRAM Vmin shift considerations in scaled HKMG technologies. - S. Balasubramanian; Vivek Joshi; Torsten Klick; Randy W. Mann; Joseph Versaggi; Akhilesh Gautam; C. Weintraub; G. Kurz; G. Krause; Andreas Kerber; Biju Parameshwaran; Tanya Nigam (CICC, 2014)

Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing. - Yoann Mamy Randriamihaja; William McMahon; S. Balasubramanian; Tanya Nigam; Biju Parameshwaran; Randy W. Mann; Torsten Klick; T. Schaefer; A. Kumar; Y. Song; Vivek Joshi; Rakesh Ranjan; et al. (IRPS, 2015)

Novel Back Gate Doping Ultra Low Retention Power 22nm FDSOl SRAM for IOT Application. - Mingcheng Chang; Nigel Chan; Vivek Joshi; Sandra Hecker; Udo Ziller; Petra Poth; Alban Zaka; Tom Herrmann; Seunghwan Seo; Hongsik Yoon; Xin Zou; Zhen Xu; et al. (ESSDERC, 2018)

Simulation Based Assessment of SRAM Data Retention Voltage. - Zhipeng Dong; Xi Cao; M. Ahosan Ul Karim; Vivek Joshi; Torsten Klick; Joerg Schmid (ISQED, 2019)