A 16 kb 1T1C FeRAM test chip using current-based reference scheme. - Joseph Wai Kit Siu; Yadollah Eslami; Ali Sheikholeslami; P. Glenn Gulak; Toru Endo; Shoichiro Kawashima (CICC, 2002)

Bitline GND sensing technique for low-voltage operation FeRAM. - Shoichiro Kawashima; Toru Endo; Akira Yamamoto; Ken-ichi Nakabayashi; Mitsuharu Nakazawa; Keizo Morita; Masaki Aoki (IEEE J. Solid State Circuits, 2002)

A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories. - Joseph Wai Kit Siu; Yadollah Eslami; Ali Sheikholeslami; P. Glenn Gulak; Toru Endo; Shoichiro Kawashima (IEEE J. Solid State Circuits, 2003)

Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM). - Yadollah Eslami; Ali Sheikholeslami; Shoichi Masui; Toru Endo; Shoichiro Kawashima (IEEE J. Solid State Circuits, 2004)

A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip. - Shoichiro Kawashima; Isao Fukushi; Keizo Morita; Ken-ichi Nakabayashi; Mitsuharu Nakazawa; Kazuaki Yamane; Tomohisa Hirayama; Toru Endo (IEICE Trans. Electron., 2007)