Adaptive Porting of Analog IPs with Reusable Conservative Properties. - Takashi Nojima; Nobuto Ono; Shigetoshi Nakatake; Toru Fujimura; Koji Okazaki; Yoji Kajitani (ISVLSI, 2006)

Transistor-level programmable MOS analog IC with body biasing. - Toru Fujimura; Shigetoshi Nakatake (ISCAS, 2008)

D-A converter based variation analysis for analog layout design. - Bo Liu 031; Toru Fujimura; Bo Yang 004; Shigetoshi Nakatake (ASP-DAC, 2010)

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. - Gong Chen 002; Toru Fujimura; Qing Dong 002; Shigetoshi Nakatake; Bo Yang 004 (ACM Trans. Design Autom. Electr. Syst., 2016)