An experimental 1.5-V 64-Mb DRAM. - Yoshinobu Nakagome; Hitoshi Tanaka; Kan Takeuchi; Eiji Kume; Yasushi Watanabe; Toru Kaga; Yoshifumi Kawamoto; Fumio Murai; Ryuichi Izawa; Digh Hisamoto; Teruaki Kisu; Takashi Nishida; et al. (IEEE J. Solid State Circuits, 1991)

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. - Yoshinobu Nakagome; Kiyoo Itoh 001; Kan Takeuchi; Eiji Kume; Hitoshi Tanaka; Masanori Isoda; Tatsunori Musha; Toru Kaga; Teruaki Kisu; Takashi Nishida; Yoshifumi Kawamoto; Masakazu Aoki (IEEE J. Solid State Circuits, 1991)

A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture. - Katsutaka Kimura; Takeshi Sakata; Kiyoo Itoh 001; Toru Kaga; Takashi Nishida; Yoshifumi Kawamoto (IEEE J. Solid State Circuits, 1991)

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. - Takeshi Sakata; Masashi Horiguchi; Tomonori Sekiguchi; Shigeki Ueda; Hitoshi Tanaka; Eiji Yamasaki; Yoshinobu Nakagome; Masakazu Aoki; Toru Kaga; Makoto Ohkura; Ryo Nagai; Fumio Murai; et al. (IEEE J. Solid State Circuits, 1995)