Built-in self-test in a 24 bit floating point digital signal processor. - Narumi Sakashita; Hisako Sawai; Eiichi Teraoka; Toshiki Fugiyama; Toru Kengaku; Yukihiko Shimazu; Takeshi Tokuda (ITC, 1990)

A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC. - Eiichi Teraoka; Toru Kengaku; Ikuo Yasui; Kazuyuki Ishikawa; Takahiro Matsuo; Hideyuki Wakada; Narumi Sakashita; Yukihiko Shimazu; Takeshi Tokuda (ITC, 1993)

A dual-issue RISC processor for multimedia signal processing. - Hisakazu Sato; Edgar Holmann; Toyohiko Yoshida; Masahito Matsuo; Toru Kengaku (ICASSP, 1997)

A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS. - Kenichi Iwata; Seiji Mochizuki; Motoki Kimura; Tetsuya Shibayama; Fumitaka Izuhara; Hiroshi Ueda; Koji Hosogi; Hiroaki Nakata; Masakazu Ehama; Toru Kengaku; Takuichiro Nakazawa; Hiromi Watanabe (IEEE J. Solid State Circuits, 2009)