ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. - Keisuke Inoue; Toru Kisuki; Michitaka Okuno; Etsuko Shimizu; Takuya Terasawa; Hideharu Amano (FPL, 1996)

Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. - Toru Kisuki; Masaki Wakabayashi; Junji Yamamoto; Keisuke Inoue; Hideharu Amano (Euro-Par, 1997)

OCEANS - Optimising Compilers for Embedded Applications. - Michel Barreteau; François Bodin; Zbigniew Chamski; Henri-Pierre Charles; Christine Eisenbeis; John R. Gurd; Jan Hoogerbrugge; Ping Hu; William Jalby; Toru Kisuki; Peter M. W. Knijnenburg; Paul van der Mark; et al. (Euro-Par, 1999)

A Feasibility Study in Iterative Compilation. - Toru Kisuki; Peter M. W. Knijnenburg; Michael F. P. O'Boyle; François Bodin; Harry A. G. Wijshoff (ISHPC, 1999)

Cache Models for Iterative Compilation. - Peter M. W. Knijnenburg; Toru Kisuki; Kyle A. Gallivan (Euro-Par, 2001)

Iterative Compilation. - Peter M. W. Knijnenburg; Toru Kisuki; Michael F. P. O'Boyle (Embedded Processor Design Challenges, 2002)

Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation. - Peter M. W. Knijnenburg; Toru Kisuki; Michael F. P. O'Boyle (J. Supercomput., 2003)

The effect of cache models on iterative compilation for combined tiling and unrolling. - Peter M. W. Knijnenburg; Toru Kisuki; Kyle A. Gallivan; Michael F. P. O'Boyle (Concurr. Comput. Pract. Exp., 2004)