An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. - Junichiro Kadomoto; Toru Koizumi 001; Akifumi Fukuda; Reoma Matsuo; Susumu Mashimo; Akifumi Fujita; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (FPT, 2018)

Reduction of Instruction Increase Overhead by STRAIGHT Compiler. - Toru Koizumi 001; Satoshi Nakae; Akifumi Fukuda; Hidetsugu Irie; Shuichi Sakai (CANDAR Workshops, 2018)

STRAIGHT: Hazardless Processor Architecture Without Register Renaming. - Hidetsugu Irie; Toru Koizumi 001; Akifumi Fukuda; Seiya Akaki; Satoshi Nakae; Yutaro Bessho; Ryota Shioya; Takahiro Notsu; Katsuhiro Yoda; Teruo Ishihara; Shuichi Sakai (MICRO, 2018)

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. - Susumu Mashimo; Koji Inoue; Ryota Shioya; Akifumi Fujita; Reoma Matsuo; Seiya Akaki; Akifumi Fukuda; Toru Koizumi 001; Junichiro Kadomoto; Hidetsugu Irie; Masahiro Goshima (FPT, 2019)

A High-Performance Out-of-Order Soft Processor Without Register Renaming. - Satoshi Mitsuno; Junichiro Kadomoto; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (FPL, 2020)

Compiling and Optimizing Real-world Programs for STRAIGHT ISA. - Toru Koizumi 001; Shu Sugita; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. - Yuya Degawa; Toru Koizumi 001; Tomoki Nakamura; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

T-SKID: Predicting When to Prefetch Separately from Address Prediction. - Toru Koizumi 001; Tomoki Nakamura; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (DATE, 2022)

A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. - Shu Sugita; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (CC, 2023)

An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. - Taichi Amano; Junichiro Kadomoto; Satoshi Mitsuno; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (ISCAS, 2023)

Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. - Toru Koizumi 001; Ryota Shioya; Shu Sugita; Taichi Amano; Yuya Degawa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (MICRO, 2023)

A Principal Factor of Performance in Decoupled Front-End. - Yuya Degawa; Toru Koizumi 001; Tomoki Nakamura; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEICE Trans. Inf. Syst., 2023)

TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA. - Reoma Matsuo; Toru Koizumi 001; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEEE Comput. Archit. Lett., 2024)

Trailing-Ones Anticipation for Reducing the Latency of the Rounding Incrementer in FP FMA Units. - Toru Koizumi 001; Ryota Shioya; Takuya Yamauchi; Tomoya Adachi; Ken Namura; Jun Makino (ARITH, 2025)

Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA. - Reoma Matsuo; Toru Koizumi 001; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEICE Trans. Inf. Syst., 2025)