A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture. - Masato Matsumiya; Shoichiro Kawashima; Makoto Sakata; Masahiko Ookura; Toru Miyabo; Tom Koga; Kazuo Itabashi; Kazuhiro Mizutani; Hiroshi Shimada; Noriyuki Suzuki (IEEE J. Solid State Circuits, 1992)