A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. - Toru Nakura; Kimio Ueda; Kazuo Kubo; Yoshio Matsuda; Koichiro Mashiko; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2000)

Theoretical study of stubs for power line noise reduction [LSI applications]. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (CICC, 2003)

Autonomous di/dt noise control scheme for margin aware operation. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2005)

Stub vs. Capacitor for Power Supply Noise Reduction. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2005)

On-chip di/dt Detector Circuit. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2005)

Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2005)

Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2006)

Autonomous di/dt Control of Power Supply for Margin Aware Operation. - Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2006)

Design of Active Substrate Noise Canceller using Power Supply di/dt Detector. - Taisuke Kazama; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2007)

LAGS System Using Data/Instruction Grain Power Control. - Makoto Ikeda; Taku Sogabe; Ken Ishii; Masayuki Mizuno; Toru Nakura; Koichi Nose; Kunihiro Asada (ISSCC, 2007)

Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. - Toru Nakura; Koichi Nose; Masayuki Mizuno (ISSCC, 2007)

Measurement of power supply noise tolerance of self-timed processor. - Kunihiro Asada; Taku Sogabe; Toru Nakura; Makoto Ikeda (DDECS, 2009)

All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. - Sanad Bushnaq; Toru Nakura; Makoto Ikeda; Kunihiro Asada (DDECS, 2009)

SAT-based ATPG testing of inter- and intra-gate bridging faults. - Toru Nakura; Yutaro Tatemura; Görschwin Fey; Makoto Ikeda; Satoshi Komatsu; Kunihiro Asada (ECCTD, 2009)

647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. - Benjamin Stefan Devlin; MyeongGyu Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2009)

Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature. - MyeongGyu Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ACM Great Lakes Symposium on VLSI, 2009)

Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability. - Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2009)

Cascaded time difference amplifier using differential logic delay cell. - Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2010)

Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects. - Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (DDECS, 2010)

All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter. - Tetsuya Iizuka; Jaehyun Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2010)

Time-to-digital converter based on time difference amplifier with non-linearity calibration. - Shingo Mandai; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2010)

A 8bit two stage time-to-digital converter using time difference amplifier. - Shingo Mandai; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Electron. Express, 2010)

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. - Benjamin Stefan Devlin; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Time Difference Amplifier with Robust Gain Using Closed-Loop Control. - Toru Nakura; Shingo Mandai; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2010)

All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter. - Jaehyun Jeong; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada (ASP-DAC, 2011)

Decoupling capacitance boosting for on-chip resonant supply noise reduction. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (DDECS, 2011)

On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2011)

Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy. - Teruki Nakasato; Toru Nakura; Kunihiro Asada (ISOCC, 2011)

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter. - Tetsuya Iizuka; Jaehyun Jeong; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells. - Shingo Mandai; Tetsuya Iizuka; Toru Nakura; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

Cascaded Time Difference Amplifier with Differential Logic Delay Cell. - Shingo Mandai; Toru Nakura; Tetsuya Iizuka; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

Impact of All-Digital PLL on SoC Testing. - Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (Asian Test Symposium, 2012)

7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage. - Toru Nakura; Yoshio Mita; Tetsuya Iizuka; Kunihiro Asada (CICC, 2012)

Power integrity control of ATE for emulating power supply fluctuations on customer environment. - Masahiro Ishida; Toru Nakura; Toshiyuki Kikkawa; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (ITC, 2012)

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2012)

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme. - Kazutoshi Kodama; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2012)

Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter. - Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2012)

An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator. - Tetsuya Iizuka; Teruki Someya; Toru Nakura; Kunihiro Asada (CICC, 2013)

A Pulse Width controlled PLL and its automated design flow. - Norihito Tohge; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2013)

Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator. - Tomohiko Yano; Toru Nakura; Kunihiro Asada (ICECS, 2013)

On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems. - Jinmyoung Kim; Toru Nakura; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2013)

Burst-pulse Generator based on transmission line toward sub-MMW. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Toru Nakura; Kunihiro Asada (DDECS, 2014)

Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits. - Kevin Ngari Muriithi; Toru Nakura; Kunihiro Asada (DDECS, 2014)

Streaming distribution of a live seminar: Rudimentary knowledge for LSI design. - Toru Nakura; Kunihiro Asada (EWME, 2014)

Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills. - Masahiro Ishida; Takashi Kusaka; Toru Nakura; Satoshi Komatsu; Kunihiro Asada (ITC, 2014)

A calibration-free time difference accumulator using two pulses propagating on a single buffer ring. - Tomohiko Yano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (A-SSCC, 2015)

A Technique for Analyzing On-Chip Power Supply Impedance. - Masahiro Ishida; Toru Nakura; Akira Matsukawa; Rimon Ikeno; Kunihiro Asada (ATS, 2015)

An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors. - Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (DDECS, 2015)

Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator. - Takashi Toi; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (NORCAS, 2015)

Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline. - Toru Nakura; Hiroaki Matsui; Kunihiro Asada (IEICE Electron. Express, 2015)

Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer. - Toru Nakura; Masahiro Kano; Masamitsu Yoshizawa; Atsunori Hattori; Kunihiro Asada (IEICE Trans. Electron., 2015)

A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse. - Tetsuya Iizuka; Takehisa Koga; Toru Nakura; Kunihiro Asada (A-SSCC, 2016)

Analytical design optimization of sub-ranging ADC based on stochastic comparator. - Md. Maruf Hossain; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (DATE, 2016)

A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. - Tetsuya Iizuka; Norihito Tohge; Satoshi Miura; Yoshimichi Murakami; Toru Nakura; Kunihiro Asada (ESSCIRC, 2016)

One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise. - Toru Nakura; Yuki Okamoto; Yoshio Mita; Kunihiro Asada (EWME, 2016)

Resonant power supply noise reduction using a triangular active charge injection. - Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2016)

Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise. - Masahiro Kano; Toru Nakura; Kunihiro Asada (ISQED, 2016)

Fully automated PLL compiler generating final GDS from specification. - Toru Nakura; Kunihiro Asada (ISQED, 2016)

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. - Toru Nakura; Naoki Terao; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (ITC, 2016)

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing. - Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (J. Electron. Test., 2016)

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing. - Masahiro Ishida; Toru Nakura; Takashi Kusaka; Satoshi Komatsu; Kunihiro Asada (IEICE Trans. Electron., 2016)

An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface. - Toshiyuki Kikkawa; Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2016)

An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors. - Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (J. Circuits Syst. Comput., 2016)

CMOS-on-quartz pulse generator for low power applications. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (ASP-DAC, 2017)

A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout. - Xiao Yang; Hongbo Zhu; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ASP-DAC, 2017)

High Spatial Resolution Detection Method for Point Light Source in Scintillator. - Kai Xu; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (Computational Imaging, 2017)

Extension of power supply impedance emulation method on ATE for multiple power domain. - Naoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (ETS, 2017)

An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration. - Ryuichi Enomoto; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (ICECS, 2017)

A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator. - Takaaki Ito; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (ICECS, 2017)

A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression. - Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (ICECS, 2017)

A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector. - Xiao Yang; Kai Xu; Tetsuya Iizuka; Toru Nakura; Hongbo Zhu; Kunihiro Asada (IEEE SENSORS, 2017)

Impulse signal generator based on current-mode excitation and transmission line resonator. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (NEWCAS, 2017)

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR. - Parit Kanjanavirojkul; Nguyen Ngoc Mai Khanh; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A PLL Compiler from Specification to GDSII. - Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. - Tomohiko Yano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2017)

A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion. - Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (VLSI-SoC, 2018)

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load. - Naoki Ojima; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (VLSI-SoC (Selected Papers), 2018)

Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. - Naoki Terao; Toru Nakura; Masahiro Ishida; Rimon Ikeno; Takashi Kusaka; Tetsuya Iizuka; Kunihiro Asada (J. Electron. Test., 2018)

Time-domain approach for analog circuits in deep sub-micron LSI. - Kunihiro Asada; Toru Nakura; Tetsuya Iizuka; Makoto Ikeda (IEICE Electron. Express, 2018)

Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator. - Md. Maruf Hossain; Tetsuya Iizuka; Toru Nakura; Kunihiro Asada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction. - Masahiro Kano; Toru Nakura; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2018)

Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting. - Toru Nakura; Tsukasa Kagaya; Tetsuya Iizuka; Kunihiro Asada (IEICE Trans. Electron., 2018)

Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes. - Tetsuya Iizuka; Kai Xu; Xiao Yang; Toru Nakura; Kunihiro Asada (IEICE Electron. Express, 2019)

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. - Wang Jing; Tetsuya Iizuka; Zule Xu; Toru Nakura (IEICE Electron. Express, 2019)

Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field. - Daigo Takahashi; Tetsuya Iizuka; Nguyen Ngoc Mai Khanh; Toru Nakura; Kunihiro Asada (IEEE Trans. Instrum. Meas., 2019)

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. - Ryuichi Enomoto; Tetsuya Iizuka; Takehisa Koga; Toru Nakura; Kunihiro Asada (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Density Aware Cell Library Design for Design-Technology Co-Optimization. - Shinichi Nishizawa; Toru Nakura (ISQED, 2022)

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop. - Tetsuya Iizuka; Meikan Chin; Toru Nakura; Kunihiro Asada (IEICE Trans. Electron., 2022)

Crystalline Oxide Semiconductor-based 3D Bank Memory System for Endpoint Artificial Intelligence with Multiple Neural Networks Facilitating Context Switching and Power Gating. - Yuto Yakubo; Kazuma Furutani; Kouhei Toyotaka; Haruki Katagiri; Masashi Fujita; Munehiro Kozuma; Yoshinori Ando; Yoshiyuki Kurokawa; Toru Nakura; Shunpei Yamazaki (ISSCC, 2023)

Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design. - Shinichi Nishizawa; Toru Nakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection. - Yuta Tsuchiya; Toru Nakura (IEICE Electron. Express, 2024)

A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA. - Kentaroh Katoh; Toru Nakura; Haruo Kobayashi 001 (DATE, 2025)

Optical Pulse Detection IC LIDARX Integrated in MMX-LIDAR. - Takahide Mizuno; Hirokazu Ikeda; Hiroki Senshu; Toru Nakura; Kazuhiro Umetani; Akihiro Konishi; Akihito Ogawa; Kaito Kasai; Kosuke Kawahara (IEICE Trans. Electron., 2025)