Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. - Toru Sano; Masaru Kato; Satoshi Tsutsumi; Yohei Hasegawa; Hideharu Amano (FPL, 2008)

Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors. - Takuro Nakamura; Toru Sano; Yohei Hasegawa; Satoshi Tsutsumi; Vasutan Tunbunheng; Hideharu Amano (FPT, 2008)

A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. - Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Hideharu Amano (ERSA, 2009)

Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. - Toru Sano; Yoshiki Saito; Hideharu Amano (ERSA, 2009)

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. - Shotaro Saito; Yoshinori Kohama; Yasufumi Sugimori; Yohei Hasegawa; Hiroki Matsutani; Toru Sano; Kazutaka Kasuga; Yoichi Yoshida; Kiichi Niitsu; Noriyuki Miura; Tadahiro Kuroda; Hideharu Amano (FPL, 2009)

Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. - Toru Sano; Yoshiki Saito; Masaru Kato; Hideharu Amano (FPL, 2009)

MuCCRA-3: a low power dynamically reconfigurable processor array. - Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Masayuki Kimura; Hideharu Amano (ASP-DAC, 2010)

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. - Kazuei Hironaka; Masayuki Kimura; Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Hideharu Amano (FPT, 2010)

A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications. - Hui Xu; Jun Tanabe; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Takashi Miyamori (VLSIC, 2012)

A near-future prediction method for low power consumption on a many-core processor. - Takeshi Kodaka; Akira Takeda; Shunsuke Sasaki; Akira Yokosawa; Toshiki Kizu; Takahiro Tokuyoshi; Hui Xu; Toru Sano; Hiroyuki Usui; Jun Tanabe; Takashi Miyamori; Nobu Matsumoto (DATE, 2013)

Development of low power many-core SoC for multimedia applications. - Takashi Miyamori; Hui Xu; Takeshi Kodaka; Hiroyuki Usui; Toru Sano; Jun Tanabe (DATE, 2013)

An evaluation of an energy efficient many-core SoC with parallelized face detection. - Hiroyuki Usui; Jun Tanabe; Toru Sano; Hui Xu; Takashi Miyamori (ASP-DAC, 2014)

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters. - Takashi Miyamori; Hui Xu; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Jun Tanabe (IEICE Trans. Electron., 2014)

18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications. - Jun Tanabe; Toru Sano; Yutaka Yamada; Tomoki Watanabe; Mayu Okumura; Manabu Nishiyama; Tadakazu Nomura; Kazushige Oma; Nobuhiro Sato; Moriyasu Banno; Hiroo Hayashi; Takashi Miyamori (ISSCC, 2015)

On Estimation of Tangential Force in Railways Brake Systems by Fuzzy Inference. - Toru Sano; Yasunori Endo; Shin-ichi Nakazawa; Daisuke Hijikata (J. Adv. Comput. Intell. Intell. Informatics, 2015)

A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. - Yutaka Yamada; Toru Sano; Yasuki Tanabe; Yutaro Ishigaki; Soichiro Hosoda; Fumihiko Hyuga; Akira Moriya; Ryuji Hada; Atsushi Masuda; Masato Uchiyama; Tomohiro Koizumi; Takanori Tamai; et al. (ISSCC, 2019)

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. - Yutaka Yamada; Masato Uchiyama; Masashi Jobashi; Tomohiro Koizumi; Takanori Tamai; Nobuhiro Sato; Jun Tanabe; Katsuyuki Kimura; Yoshinari Ojima; Ryusuke Murakami; Takashi Yoshikawa; Toru Sano; et al. (IEEE J. Solid State Circuits, 2020)