A 32-bit microprocessor with high performance bit-map manipulation instructions. - Toru Shimizu; Shunichi Iwata; Yuichi Saito; Toyohiko Yoshida; Masahito Matsuo; Junichi Hinata; Kazunori Saito (ICCD, 1989)

M32R/D-integrating DRAM and microprocessor. - Yasuhiro Nunomura; Toru Shimizu; Osamu Tomisawa (IEEE Micro, 1997)

Multimedia applications of microprocessor with embedded DRAM. - Yasuhiro Nunomura; Toru Shimizu; Kazunori Saitoh; Koji Tsuchihashi (ICASSP, 1998)

A new RISC processor architecture for MPEG-2 decoding. - Kunihiro Yamada; Masanori Kojima; Toru Shimizu; Fumiaki Sato; Tadanori Mizuno (IEEE Trans. Consumer Electron., 2002)

Dual Communication System Using Wired and Wireless Correspondence in a Small Space. - Kunihiro Yamada; Yoshihiko Hirata; Yukihisa Naoe; Takashi Furumura; Yoshio Inoue; Toru Shimizu; Koji Yoshida; Masanori Kojima; Tadanori Mizuno (KES, 2004)

A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. - Satoshi Kaneko; Hiroyuki Kondo; Norio Masui; Koichi Ishimi; Teruyuki Itou; Masayuki Satou; Naoto Okumura; Yukari Takata; Hirokazu Takata; Mamoru Sakugawa; Takashi Higuchi; Sugako Ohtani; et al. (IEEE J. Solid State Circuits, 2004)

Dual Communication System Using Wired and Wireless with the Routing Consideration. - Kunihiro Yamada; Takashi Furumura; Yoshio Inoue; Kenichi Kitazawa; Hiroki Takase; Yukihisa Naoe; Toru Shimizu; Yoshihiko Hirata; Hiroshi Mineno; Tadanori Mizuno (KES (1), 2005)

Dual Communication System Using Wired and Wireless Correspondence in Home Network. - Kunihiro Yamada; Kenichi Kitazawa; Hiroki Takase; Toshihiko Tamura; Yukihisa Naoe; Takashi Furumura; Toru Shimizu; Koji Yoshida; Masanori Kojima; Tadanori Mizuno (KES (1), 2005)

Implementation of Face Recognition Processing Using an Embedded Processor. - Hiroyuki Kondo; Masami Nakajima; Miroslaw Bober; Krzysztof Kucharski; Osamu Yamamoto; Toru Shimizu (J. Robotics Mechatronics, 2005)

A 40GOPS 250mW massively parallel processor based on matrix architecture. - Masami Nakajima; Hideyuki Noda; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Hiroyuki Kondo; Yukihiko Shimazu; Kazutami Arimoto; Kazunori Saitoh; Toru Shimizu (ISSCC, 2006)

Spatial Relation for Geometrical / Topological Map Retrieval. - Toru Shimizu; Masakazu Ikezaki; Toyohide Watanabe; Taketoshi Ushiama (KES (2), 2006)

Home-Network of a Mutual Complement Communication System by Wired and Wireless. - Kunihiro Yamada; Takashi Furumura; Yasuhiro Seno; Yukihisa Naoe; Kenichi Kitazawa; Toru Shimizu; Koji Yoshida; Masanori Kojima; Hiroshi Mineno; Tadanori Mizuno (KES (3), 2006)

Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture. - Toru Shimizu; Masami Nakajima; Masahiro Kainaga (IEICE Trans. Electron., 2006)

SE4 Automotive Signal Processing Technologies. - Toru Shimizu; Ram Krishnamurthy 001 (ISSCC, 2007)

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. - Kazutami Arimoto; Toshihiro Hattori; Hidehiro Takata; Atsushi Hasegawa; Toru Shimizu (IEICE Trans. Electron., 2007)

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Masami Nakajima; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Tetsushi Tanizaki; Takayuki Gyohten; Yoshihiro Okuno; Hiroyuki Kondo; Yukihiko Shimazu; et al. (IEEE J. Solid State Circuits, 2007)

Heterogeneous multicore SoC for secure multimedia applications. - Hiroyuki Kondo; Masami Nakajima; Sugako Otani; Osamu Yamamoto; Norio Masui; Naoto Okumura; Mamoru Sakugawa; Masaya Kitao; Koichi Ishimi; Masayuki Sato; Fumitaka Fukuzawa; Kazuhiro Inaoka; et al. (CICC, 2008)

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. - Hiroyuki Kondo; Sugako Otani; Masami Nakajima; Osamu Yamamoto; Norio Masui; Naoto Okumura; Mamoru Sakugawa; Masaya Kitao; Koichi Ishimi; Masayuki Sato; Fumitaka Fukuzawa; Satoshi Imasu; et al. (IEEE J. Solid State Circuits, 2009)

0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers. - Yasunobu Nakase; Shinichi Hirose; Toru Goda; Kehui Hu; Hiroshi Onoda; Yasuhiro Ido; Hiroyuki Kondo; Wei Kong; Wei Zhang; Tsukasa Oishi; Shintaro Mori; Toru Shimizu (A-SSCC, 2011)

Low Power Platform for Embedded Processor LSIs. - Toru Shimizu; Kazutami Arimoto; Osamu Nishii; Sugako Otani; Hiroyuki Kondo (IEICE Trans. Electron., 2011)

A 0.5V start-up 87% efficiency 0.75mm2 on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration. - Yasunobu Nakase; Shinichi Hirose; Hiroshi Onoda; Yasuhiro Ido; Yoshiaki Shimizu; Tsukasa Oishi; Toshio Kumamoto; Toru Shimizu (CICC, 2012)

Large-scale network organization in the avian forebrain: a connectivity matrix and theoretical analysis. - Murray Shanahan; Verner P. Bingman; Toru Shimizu; Martin Wild; Onur Güntürkün (Frontiers Comput. Neurosci., 2013)

On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes. - Yasunobu Nakase; Yasuhiro Ido; Tsukasa Oishi; Toru Shimizu (IEICE Trans. Electron., 2013)

0.5 V Start-Up 87% Efficiency 0.75 mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration. - Yasunobu Nakase; Shinichi Hirose; Hiroshi Onoda; Yasuhiro Ido; Yoshiaki Shimizu; Tsukasa Oishi; Toshio Kumamoto; Toru Shimizu (IEEE J. Solid State Circuits, 2013)

Normally-off MCU architecture for low-power sensor node. - Masanori Hayashikoshi; Yohei Sato; Hiroshi Ueki; Hiroyuki Kawai; Toru Shimizu (ASP-DAC, 2014)

What is a good way to expand a silicon value to a solution value? - Tzi-Dar Chiueh; Toru Shimizu; Gregory Chen; Chen-Yi Lee; Charles Hsu; Tihao Chiang; Zhihua Wang 001; Junghwan Choi; Jongwoo Lee; Yasumoto Tomita; Takayuki Kawahara (A-SSCC, 2014)

A low power NoC router using the marching memory through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (COOL Chips, 2014)

Design of a low power NoC router using Marching Memory Through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (NOCS, 2014)

Data-aware power management for periodic real-time systems with non-volatile memory. - Takashi Nakada; Takuya Shigematsu; Toshiya Komoda; Shinobu Miwa; Hiroshi Nakamura; Yohei Sato; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu (NVMSA, 2014)

Design Aid of Multi-core Embedded Systems with Energy Model. - Takashi Nakada; Kazuya Okamoto; Toshiya Komoda; Shinobu Miwa; Yohei Sato; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu; Hiroshi Nakamura (Inf. Media Technol., 2014)

Normally-off power management for sensor nodes of global navigation satellite system. - Takashi Nakada; Hiroshi Nakamura; Toshifumi Nakamoto; Toru Shimizu (ISOCC, 2016)

Deep learning application trial to lung cancer diagnosis for medical sensor systems. - Ryota Shimizu; Shusuke Yanagawa; Yasutaka Monde; Hiroki Yamagishi; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (ISOCC, 2016)

An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. - Takashi Nakada; Tomoki Hatanaka; Hiroshi Nakamura; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu (VLSI-SoC, 2016)

Convolutional neural network for industrial egg classification. - Ryota Shimizu; Shusuke Yanagawa; Toru Shimizu; Mototsugu Hamada; Tadahiro Kuroda (ISOCC, 2017)

Wireless power transfer to stacked modules for IoT sensor nodes. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (ISOCC, 2017)

YJTI at the NTCIR-13 STC Japanese Subtask. - Toru Shimizu (NTCIR, 2017)

An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation. - Takashi Nakada; Tomoki Hatanaka; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu; Hiroshi Nakamura (IEICE Trans. Inf. Syst., 2017)

Pretraining Sentiment Classifiers with Unlabeled Dialog Data. - Toru Shimizu; Nobuyuki Shimizu; Hayato Kobayashi (ACL (2), 2018)

Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (ISCAS, 2018)

Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers. - Shusuke Yanagawa; Ryota Shimizu; Mototsugu Hamada; Toru Shimizu; Tadahiro Kuroda (IEICE Trans. Electron., 2018)

Unsupervised Answer Retrieval with Data Fusion for Community Question Answering. - Sosuke Kato; Toru Shimizu; Sumio Fujita; Tetsuya Sakai (AIRS, 2019)

City2City: Translating Place Representations across Cities. - Takahiro Yabe; Kota Tsubouchi; Toru Shimizu; Yoshihide Sekimoto; Satish V. Ukkusuri (SIGSPATIAL/GIS, 2019)

Predicting Evacuation Decisions using Representations of Individuals' Pre-Disaster Web Search Behavior. - Takahiro Yabe; Kota Tsubouchi; Toru Shimizu; Yoshihide Sekimoto; Satish V. Ukkusuri (KDD, 2019)

Enabling Finer Grained Place Embeddings using Spatial Hierarchy from Human Mobility Trajectories. - Toru Shimizu; Takahiro Yabe; Kota Tsubouchi (SIGSPATIAL/GIS, 2020)

POI Atmosphere Categorization Using Web Search Session Behavior. - Kota Tsubouchi; Hayato Kobayashi; Toru Shimizu (SIGSPATIAL/GIS, 2020)

Unsupervised Translation via Hierarchical Anchoring: Functional Mapping of Places across Cities. - Takahiro Yabe; Kota Tsubouchi; Toru Shimizu; Yoshihide Sekimoto; Satish V. Ukkusuri (KDD, 2020)

Learning Fine Grained Place Embeddings with Spatial Hierarchy from Human Mobility Trajectories. - Toru Shimizu; Takahiro Yabe; Kota Tsubouchi (CoRR, 2020)

Improving Land Use Classification using Human Mobility-based Hierarchical Place Embeddings. - Toru Shimizu; Takahiro Yabe; Kota Tsubouchi (PerCom Workshops, 2021)

GEO-BLEU: similarity measure for geospatial sequences. - Toru Shimizu; Kota Tsubouchi; Takahiro Yabe (SIGSPATIAL/GIS, 2022)

Metropolitan Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories. - Takahiro Yabe; Kota Tsubouchi; Toru Shimizu; Yoshihide Sekimoto; Kaoru Sezaki; Esteban Moro; Alex Pentland (CoRR, 2023)

Human Mobility Prediction Challenge 2023. - Takahiro Yabe; Kota Tsubouchi; Toru Shimizu; Yoshihide Sekimoto; Kaoru Sezaki; Esteban Moro; Alex Pentland (Zenodo, 2023)

YJMob100K: City-Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories. - Takahiro Yabe; Kota Tsubouchi; Toru Shimizu; Yoshihide Sekimoto; Kaoru Sezaki; Esteban Moro; Alex Pentland (Zenodo, 2023)

YJMob100K: City-Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories. - Takahiro Yabe; Kota Tsubouchi; Toru Shimizu; Yoshihide Sekimoto; Kaoru Sezaki; Esteban Moro; Alex Pentland (Zenodo, 2024)