Single-electron memory for giga-to-tera bit storage. - Kazuo Yano; Tomoyuki Ishii; Toshiaki Sano; Toshiyuki Mine; Fumio Murai; Takashi Hashimoto; Takashi Kobayashi 002; Tokuo Kure; Koichi Seki (Proc. IEEE, 1999)

SESO memory: A 3T gain cell solution using ultra thin silicon film for dense and low power embedded memories. - Tomoyuki Ishii; Taro Osabe; Toshiyuki Mine; Toshiaki Sano; Bryan Atwood; Norifumi Kameshiro; Takao Watanabe; Kazuo Yano (CICC, 2004)

A cavity channel SESO embedded memory with low standby-power techniques. - Bryan Atwood; Tomoyuki Ishii; Takao Watanabe; Toshiyuki Mine; Norifumi Kameshiro; Toshiaki Sano; Kazuo Yano (ESSCIRC, 2004)

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. - Shinji Tanaka; Yuichiro Ishii; Makoto Yabuuchi; Toshiaki Sano; Koji Tanaka; Yasumasa Tsukamoto; Koji Nii; Hirotoshi Sato (VLSIC, 2014)

A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. - Yuichiro Ishii; Makoto Yabuuchi; Yohei Sawada; Masao Morimoto; Yasumasa Tsukamoto; Yuta Yoshida; Ken Shibata; Toshiaki Sano; Shinji Tanaka; Koji Nii (A-SSCC, 2016)

A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time. - Makoto Yabuuchi; Yohei Sawada; Toshiaki Sano; Yuichiro Ishii; Shinji Tanaka; Miki Tanaka; Koji Nii (VLSI Circuits, 2016)