A built-in Hamming code ECC circuit for DRAMs. - Kiyohiro Furutani; Kazutami Arimoto; Hiroshi Miyamoto; Toshifumi Kobayashi; Kenichi Yasuda; Koichiro Mashiko (IEEE J. Solid State Circuits, 1989)

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure. - Tadato Yamagata; Masaaki Mihara; Takeshi Hamamoto; Yasumitsu Murai; Toshifumi Kobayashi; Michihiro Yamada; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1992)

A method of shortening metastable operation duration time by the use of feedback. - Yoichiro Sato; Takuji Okamoto; Yuji Sugiyama; Masahiro Kawai; Toshifumi Kobayashi (Syst. Comput. Jpn., 1996)

CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply. - Hiroyuki Michinishi; Tokumi Yokohira; Takuji Okamoto; Toshifumi Kobayashi; Tsutomu Hondo (Asian Test Symposium, 2002)

Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test. - Hiroyuki Michinishi; Tokumi Yokohira; Takuji Okamoto; Toshifumi Kobayashi; Tsutomu Hondo (Asian Test Symposium, 2003)

CMOS Floating Gate Defect Detection Using Supply Current Test with DC Power Supply Superposed by AC Component. - Hiroyuki Michinishi; Tokumi Yokohira; Takuji Okamoto; Toshifumi Kobayashi; Tsutomu Hondo (IEICE Trans. Inf. Syst., 2004)

Detection of CMOS Open Node Defects by Frequency Analysis. - Hiroyuki Michinishi; Tokumi Yokohira; Takuji Okamoto; Toshifumi Kobayashi; Tsutomu Hondo (IEICE Trans. Inf. Syst., 2007)