A New Design Concept for Balanced-Type SAW Filters Using a Common-Mode Signal Suppression Circuit. - Hiroyuki Nakamura; Toshio Ishizaki; Toshifumi Nakatani; Shigeru Tsuzuki (IEICE Trans. Electron., 2005)

IM3 Cancellation Method Using Current Feedback Suitable for a Multi-Stage RFIC Amplifier. - Toshifumi Nakatani; Koichi Ogawa (IEICE Trans. Electron., 2007)

A Low Distortion and Low Noise Differential Amplifier Suitable for 3G LTE Applications Using the Even- and Odd-Mode Impedance Differences of a Bias Circuit. - Toshifumi Nakatani; Koichi Ogawa (IEICE Trans. Electron., 2008)

Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications. - Toshifumi Nakatani; Jeremy Rode; Donald F. Kimball; Lawrence E. Larson; Peter M. Asbeck (IEEE J. Solid State Circuits, 2012)

A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications. - Takayuki Tsukizawa; Naganori Shirakata; Tadashi Morita; Koichiro Tanaka; Junji Sato; Yohei Morishita; Masaki Kanemaru; Ryo Kitamura; Takahiro Shima; Toshifumi Nakatani; Kenji Miyanaga; Tomoya Urushihara; et al. (ISSCC, 2013)

A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage. - Noriaki Saito; Takayuki Tsukizawa; Naganori Shirakata; Tadashi Morita; Koichiro Tanaka; Junji Sato; Yohei Morishita; Masaki Kanemaru; Ryo Kitamura; Takahiro Shima; Toshifumi Nakatani; Kenji Miyanaga; et al. (IEEE J. Solid State Circuits, 2013)

A 1-3 GHz Delta-Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI. - Hamed Gheidi; Toshifumi Nakatani; Vincent W. Leung; Peter M. Asbeck (IEEE J. Solid State Circuits, 2017)

A 29-dBm, 34% PAE E-Band Dual-Input Doherty Power Amplifier Using 40-nm GaN Technology. - Toshifumi Nakatani; Mohammad Ali Zolfaghari; Jonmei J. Yan; Peter M. Asbeck (BCICTS, 2022)