A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM. - Yoshihisa Iwata; Ken-ichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Hideko Oodaira; Masaki Momodomi; Yasuo Itoh; Toshiharu Watanabe; Hitoshi Araki; Kazuhito Narita; Kazunori Masuda; Junichi Miyamoto (IEEE J. Solid State Circuits, 1995)

Connectionist Abstraction for Machine Learning by Analogy. - Syozo Yasui; Toshiharu Watanabe; Hideaki Fujimura (ICONIP, 1998)

A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. - Shigeru Atsumi; Akira Umezawa; Toru Tanzawa; Tadayuki Taura; Hitoshi Shiga; Yoshinori Takano; Takeshi Miyaba; Michiharu Matsui; Hiroshi Watanabe; Kazuaki Isobe; Shota Kitamura; Seiji Yamada; et al. (IEEE J. Solid State Circuits, 2000)

Design of decision trees using class-dependent feature subsets. - Kazuaki Aoki; Toshiharu Watanabe; Mineichi Kudo (Syst. Comput. Jpn., 2005)

A 146-mm2 8-gb multi-level NAND flash memory with 70-nm CMOS technology. - Takahiko Hara; Koichi Fukuda; Kazuhisa Kanazawa; Noboru Shibata; Koji Hosono; Hiroshi Maejima; Michio Nakagawa; Takumi Abe; Masatsugu Kojima; Masaki Fujiu; Yoshiaki Takeuchi; Kazumi Amemiya; et al. (IEEE J. Solid State Circuits, 2006)

A 113mm2 32Gb 3b/cell NAND flash memory. - Takuya Futatsuyama; Norihiro Fujita; Naoya Tokiwa; Yoshihiko Shindo; Toshiaki Edahiro; Teruhiko Kamei; Hiroaki Nasu; Makoto Iwai; Koji Kato; Yasuyuki Fukuda; Naoaki Kanagawa; Naofumi Abiko; et al. (ISSCC, 2009)