A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications. - Masafumi Takahashi; Tsuyoshi Nishikawa; Hideho Arakida; Noriaki Machida; Hideaki Yamamoto; Toshihide Fujiyoshi; Yoko Matsumoto; Osamu Yamagishi; Tatsuo Samata; Atsushi Asano; Toshihiro Terazawa; Kenji Ohmori; et al. (ISCAS, 2000)

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. - Masafumi Takahashi; Tsuyoshi Nishikawa; Mototsugu Hamada; Toshinari Takayanagi; Hideho Arakida; Noriaki Machida; Hideaki Yamamoto; Toshihide Fujiyoshi; Yoko Ohashi; Osamu Yamagishi; Tatsuo Samata; Atsushi Asano; et al. (IEEE J. Solid State Circuits, 2000)

Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI. - Yukihito Oowaki; Shinichiro Shiratake; Toshihide Fujiyoshi; Mototsugu Hamada; Fumitoshi Hatori; Masami Murakata; Masafumi Takahashi (IEICE Trans. Electron., 2006)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)