A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture. - Toshihiko Hirose; Hirotada Kuriyama; Shuji Murakami; Kojiro Yuzuriha; Takao Mukai; Kazuhito Tsutsumi; Yasumasa Nishimura; Yoshio Kohno; Kenji Anami (IEEE J. Solid State Circuits, 1990)

An 8 ns 4 Mb serial access memory. - Hirotada Kuriyama; Toshihiko Hirose; Shuji Murakami; Tomohisa Wada; Kore-aki Fujita; Yasumasa Nishimura; Kenji Anami (IEEE J. Solid State Circuits, 1991)