Logic circuits using resonant-tunneling hot-electron transistors (RHETs). - Motomu Takatsu; Kenichi Imamura; Hiroaki Ohnishi; Toshihiko Mori; Takami Adachihara; Shunichi Muto; Naoki Yokoyama (IEEE J. Solid State Circuits, 1992)

A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's. - Shoichiro Kawashima; Toshihiko Mori; Ryuhei Sasagawa; Makoto Hamaminato; Shigetoshi Wakayama; Kazuo Sukegawa; Isao Fukushi (IEEE J. Solid State Circuits, 1998)

Low-power SRAM design using half-swing pulse-mode techniques. - Kenneth W. Mai; Toshihiko Mori; Bharadwaj S. Amrutur; Ron Ho; Bennett Wilburn; Mark A. Horowitz; Isao Fukushi; Tetsuo Izawa; Shin Mitarai (IEEE J. Solid State Circuits, 1998)

Customization Rule Generation for Electronic Sales Promotion System in Wholesale Industry. - Masaki Yumoto; Kyungsuk Oh; Norihisa Komoda; Toshihiko Mori (WECWIS, 1999)

A CMOS multichannel 10-Gb/s transceiver. - Hideki Takauchi; Hirotaka Tamura; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takaya Chiba; Hideaki Anbutsu; Hisakatsu Yamaguchi; Toshihiko Mori; Motomu Takatsu; Kohtaroh Gotoh; Toshiaki Sakai; et al. (IEEE J. Solid State Circuits, 2003)

A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing. - Masato Yoshioka; Masahiro Kudo; Toshihiko Mori; Sanroku Tsukamoto (ISSCC, 2007)

Non-binary SAR ADC with digital error correction for low power applications. - Tomohiko Ogawa; Tatsuji Matsuura; Haruo Kobayashi 001; Nobukazu Takai; Masao Hotta; Hao San; Akira Abe; Katsuyoshi Yagi; Toshihiko Mori (APCCAS, 2010)

SAR ADC Algorithm with Redundancy and Digital Error Correction. - Tomohiko Ogawa; Haruo Kobayashi 001; Yosuke Takahashi; Nobukazu Takai; Masao Hotta; Hao San; Tatsuji Matsuura; Akira Abe; Katsuyoshi Yagi; Toshihiko Mori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications. - Hiroyuki Nakamoto; Masahiro Kudo; Kimitoshi Niratsuka; Toshihiko Mori; Shinji Yamaura (ESSCIRC, 2012)

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets. - Kouichi Kanda; Yoichi Kawano; Takao Sasaki; Noriaki Shirai; Tetsuro Tamura; Shigeaki Kawai; Masahiro Kudo; Tomotoshi Murakami; Hiroyuki Nakamoto; Nobumasa Hasegawa; Hideki Kano; Nobuhiro Shimazui; et al. (ISSCC, 2012)

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE. - Kazuaki Oishi; Eiji Yoshida; Yasufumi Sakai; Hideki Takauchi; Yoichi Kawano; Noriaki Shirai; Hideki Kano; Masahiro Kudo; Tomotoshi Murakami; Tetsuro Tamura; Seitaro Kawai; Shinji Yamaura; et al. (ISSCC, 2014)

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. - Takayuki Shibasaki; Win Chaivipas; Yanfei Chen; Yoshiyasu Doi; Takayuki Hamada; Hideki Takauchi; Toshihiko Mori; Yoichi Koyanagi; Hirotaka Tamura (VLSIC, 2014)

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE. - Kazuaki Oishi; Eiji Yoshida; Yasufumi Sakai; Hideki Takauchi; Yoichi Kawano; Noriaki Shirai; Hideki Kano; Masahiro Kudo; Tomotoshi Murakami; Tetsuro Tamura; Shigeaki Kawai; Kazuo Suto; et al. (IEEE J. Solid State Circuits, 2014)

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI. - Yanfei Chen; Masaya Kibune; Asako Toda; Akinori Hayakawa; Tomoyuki Akiyama; Shigeaki Sekiguchi; Hiroji Ebe; Nobuhiro Imaizumi; Tomoyuki Akahoshi; Suguru Akiyama; Shinsuke Tanaka; Takasi Simoyama; et al. (ISSCC, 2015)

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS. - Takayuki Shibasaki; Yukito Tsunoda; Hideki Oku; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Kazuhiro Tanaka; Tomohiro Ishihara; Hirotaka Tamura (ISSCC, 2015)

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS. - Yukito Tsunoda; Takayuki Shibasaki; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Kazuhiro Tanaka; Tomohiro Ishihara; Hirotaka Tamura (ISSCC, 2015)

A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects. - Akinori Hayakawa; Masaya Kibune; Asako Toda; Shinsuke Tanaka; Takasi Simoyama; Yanfei Chen; Tomoyuki Akiyama; Shigekazu Okumura; Takeshi Baba; Tomoyuki Akahoshi; Seiji Ueno; Kazunori Maruyama; et al. (OFC, 2015)

25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs. - Yukito Tsunoda; Takayuki Shibasaki; Hideki Oku; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Kazuhiro Tanaka; Tomohiro Ishihara; Hirotaka Tamura (OFC, 2015)

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. - Takayuki Shibasaki; Takumi Danjo; Yuuki Ogata; Yasufumi Sakai; Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Shigeaki Kawai; Tomoyuki Arai; Hirohito Higashi; et al. (ISSCC, 2016)

24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR. - Yukito Tsunoda; Takayuki Shibasaki; Hideki Oku; Jun Matsui; Takashi Shiraishi; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Hirotaka Tamura (OFC, 2016)

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. - Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Noriaki Shirai; Shigeaki Kawai; Takayuki Shibasaki; Takumi Danjo; Yuuki Ogata; Yasufumi Sakai; Hisakatsu Yamaguchi; et al. (VLSI Circuits, 2016)

Low Crosstalk Simultaneous 16-channel × 25 Gb/s Operation of High Density Silicon Photonics Optical Transceiver. - Tsuyoshi Aoki; Shigeaki Sekiguchi; Takasi Simoyama; Shinsuke Tanaka; Motoyuki Nishizawa; Nobuaki Hatori; Yohei Sobu; Akio Sugama; Tomoyuki Akiyama; Akinori Hayakawa; Hidenobu Muranaka; Toshihiko Mori; et al. (ECOC, 2017)

Ultra-Low-Power (1.59 mW/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach-Zehnder Modulator and 28-nm CMOS Driver. - Shinsuke Tanaka; Takasi Simoyama; Tsuyoshi Aoki; Toshihiko Mori; Shigeaki Sekiguchi; Seok-Hwan Jeong; Tatsuya Usuki; Yu Tanaka; Ken Morito (ECOC, 2017)

Low crosstalk simultaneous 12 ch × 25 Gb/s operation of high-density silicon photonics multichannel receiver. - Tsuyoshi Aoki; Tomoyuki Akiyama; Akio Sugama; Akinori Hayakawa; Hidenobu Muranaka; Takasi Simoyama; Shinsuke Tanaka; Motoyuki Nishizawa; Nobuaki Hatori; Yohei Sobu; Yanfei Chen; Toshihiko Mori; et al. (OFC, 2017)

On-Package High-Density Silicon Photonics Optical Transceiver. - Tsuyoshi Aoki; Shigeaki Sekiguchi; Takasi Simoyama; Shinsuke Tanaka; Motoyuki Nishizawa; Nobuaki Hatori; Yohei Sobu; Akio Sugama; Tomoyuki Akiyama; Akinori Hayakawa; Hidenobu Muranaka; Toshihiko Mori; et al. (ECOC, 2018)

Error-Free Loopback of a Compact 25 Gb/s × 4 ch WDM Transceiver Assembly Incorporating Silicon (De)Multiplexers with Automated Phase-Error Correction. - Tomoyuki Akiyama; Tsuyoshi Aoki; Takasi Simoyama; Akio Sugama; Shigeaki Sekiguchi; Yohei Sobu; Shinsuke Tanaka; Yu Tanaka; Seok-Hwan Jeong; Motoyuki Nishizawa; Nobuaki Hatori; Akinori Hayakawa; et al. (OFC, 2018)

Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design. - Yukito Tsunoda; Takahiro Notsu; Yasufumi Sakai; Naoki Hamada; Toshihiko Mori; Teruo Ishihara; Atsuki Inoue (GECCO (Companion), 2019)

Highly power-efficient (2 pJ/bit), 128Gbps 16QAM signal generation of coherent optical DAC transmitter using 28-nm CMOS driver and all-silicon segmented modulator. - Yohei Sobu; Guoxiu Huang; Toshihiko Mori; Yukito Tsunoda; Takuji Yamamoto; Shinsuke Tanaka; Takeshi Hoshida (OFC, 2022)

High-speed and low-power optical DAC transmitter using all-silicon lumped segmented modulator directly driven by CMOS inverter driver. - Yohei Sobu; Yukito Tsunoda; Toshihiko Mori; Guoxiu Huang; Takuji Yamamoto; Shinsuke Tanaka; Takeshi Hoshida (OFC, 2024)