Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. - Toshihiro Hattori; Yusuke Nitta; Mitsuho Seki; Susumu Narita; Kunio Uchiyama; Tsuyoshi Takahashi; Ryuichi Satomura (DAC, 1998)

An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode. - Hiroyuki Mizuno; Koichiro Ishibashi; Takanori Shimura; Toshihiro Hattori; Susumu Narita; Kenji Shiozawa; Shuji Ikeda; Kunio Uchiyama (IEEE J. Solid State Circuits, 1999)

Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. - Hidetoshi Onodera; Andrew B. Kahng; Wayne Wei-Ming Dai; Sani R. Nassif; Juho Kim; Akira Tanabe; Toshihiro Hattori (ASP-DAC, 2001)

Design methodology of low-power microprocessors. - Toshihiro Hattori (ASP-DAC, 2003)

Low-Power Design of 90-nm SuperH Processor Core. - Tetsuya Yamada; Masahide Abe; Yusuke Nitta; Kenji Ogura; Manabu Kusaoke; Makoto Ishikawa; Motokazu Ozawa; Kiwamu Takada; Fumio Arakawa; Osamu Nishii; Toshihiro Hattori (ICCD, 2005)

SH-mobile - low power application processor for cellular [3G cellular phones]. - Shoichi Kamae; Takahiro Irita; Akifumi Tsukimori; Saneaki Tarnaki; Toshihiro Hattori; Shinichi Yoshioka (ISCAS (5), 2005)

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. - Makoto Ishikawa; Tatsuya Kamei; Yuki Kondo; Masanao Yamaoka; Yasuhisa Shimazaki; Motokazu Ozawa; Saneaki Tamaki; Mikio Furuyama; Tadashi Hoshi; Fumio Arakawa; Osamu Nishii; Kenji Hirose; et al. (IEICE Trans. Electron., 2005)

SH-X: an embedded processor core for consumer appliances. - Fumio Arakawa; Makoto Ishikawa; Yuki Kondo; Tatsuya Kamei; Motokazu Ozawa; Osamu Nishii; Toshihiro Hattori (SIGARCH Comput. Archit. News, 2005)

Hierarchical power distribution and power management scheme for a single chip mobile processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (DAC, 2006)

SH-MobileG1: A single-chip application and dual-mode baseband processor. - Masayuki Ito; Takahiro Irita; Eiji Yamamoto; Kunihiko Nishiyama; Takao Koike; Yoshihiko Tsuchihashi; Hiroyuki Asano; Hiroshi Yagi; Saneaki Tamaki; Ken Tatezawa; Toshihiro Hattori; Shinichi Yoshioka; et al. (Hot Chips Symposium, 2006)

A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. - Toshihiro Hattori; Takahiro Irita; Masayuki Ito; Eiji Yamamoto; Hisashi Kato; Go Sado; Tetsuhiro Yamada; Kunihiko Nishiyama; Hiroshi Yagi; Takao Koike; Yoshihiko Tsuchihashi; Motoki Higashida; et al. (ISSCC, 2006)

Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (ISSCC, 2006)

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core. - Tetsuya Yamada; Masahide Abe; Yusuke Nitta; Kenji Ogura; Manabu Kusaoke; Makoto Ishikawa; Motokazu Ozawa; Kiwamu Takada; Fumio Arakawa; Osamu Nishii; Toshihiro Hattori (IEICE Trans. Electron., 2006)

SH-X: An embedded processor core for consumer appliances. - Fumio Arakawa; Makoto Ishikawa; Yuki Kondo; Tatsuya Kamei; Osamu Nishii; Toshihiro Hattori (J. Embed. Comput., 2006)

Development of processor cores for digital consumer appliances. - Fumio Arakawa; Tetsuya Yamada; Takashi Okada; Makoto Ishikawa; Yuki Kondo; Motokazu Ozawa; Tomoyuki Kodama; Osamu Nishii; Toshihiro Hattori; Tatsuya Kamei; Junichi Nishimoto; Shinichi Yoshioka (Syst. Comput. Jpn., 2006)

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS. - Masayuki Ito; Toshihiro Hattori; Takahiro Irita; Ken Tatezawa; Fumihito Tanaka; Kenji Hirose; Shinichi Yoshioka; Koji Ohno; Reiko Tsuchihashi; Minoru Sakata; Masayuki Yamamoto; Yuji Aral (ISSCC, 2007)

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. - Yutaka Yoshida; Tatsuya Kamei; Kiyoshi Hayase; Shinichi Shibahara; Osamu Nishii; Toshihiro Hattori; Atsushi Hasegawa; Masashi Takada; Naohiko Irie; Kunio Uchiyama; Toshihiko Odaka; Kiwamu Takada; et al. (ISSCC, 2007)

Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs. - Andrew B. Kahng; Ira Chayut; John M. Cohn; Toshihiro Hattori; Jeong-Taek Kong; Pierre G. Paulin; Rich Tobias (IEEE Des. Test Comput., 2007)

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. - Kazutami Arimoto; Toshihiro Hattori; Hidehiro Takata; Atsushi Hasegawa; Toru Shimizu (IEICE Trans. Electron., 2007)

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. - Yusuke Kanno; Hiroyuki Mizuno; Yoshihiko Yasu; Kenji Hirose; Yasuhisa Shimazaki; Tadashi Hoshi; Yujiro Miyairi; Toshifumi Ishii; Tetsuya Yamada; Takahiro Irita; Toshihiro Hattori; Kazumasa Yanagisawa; et al. (IEEE J. Solid State Circuits, 2007)

Multicore design is the challenge! what is the solution? - Eshel Haritan; Toshihiro Hattori; Hiroyuki Yagi; Pierre G. Paulin; Wayne H. Wolf; Achim Nohl; Drew Wingard; Mike Muller (DAC, 2008)

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. - Masayuki Ito; Toshihiro Hattori; Yutaka Yoshida; Kiyoshi Hayase; Tomoichi Hayashi; Osamu Nishii; Yoshihiko Yasu; Atsushi Hasegawa; Masashi Takada; Hiroyuki Mizuno; Kunio Uchiyama; Toshihiko Odaka; et al. (ISSCC, 2008)

A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU. - Masao Naruse; Tatsuya Kamei; Toshihiro Hattori; Takahiro Irita; Kenichi Nitta; Takao Koike; Shinichi Yoshioka; Koji Ohno; Masahito Saigusa; Minoru Sakata; Yukio Kodama; Yuji Arai; et al. (ISSCC, 2008)

A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management. - Tatsuya Kamei; Tetsuhiro Yamada; Takao Koike; Masayuki Ito; Takahiro Irita; Kenichi Nitta; Toshihiro Hattori; Shinichi Yoshioka (ASP-DAC, 2009)

A 342mW mobile application processor with full-HD multi-standard video codec. - Kenichi Iwata; Takahiro Irita; Seiji Mochizuki; Hiroshi Ueda; Masakazu Ehama; Motoki Kimura; Jun Takemura; Keiji Matsumoto; Eiji Yamamoto; Tadashi Teranuma; Katsuji Takakubo; Hiromi Watanabe; et al. (ISSCC, 2009)

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. - Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Makoto Saen; Shigenobu Komatsu; Kenichi Osada; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (ISSCC, 2009)

Multi-Core/Multi-IP Technology for Embedded Applications. - Naohiko Irie; Toshihiro Hattori (IEICE Trans. Electron., 2009)

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU. - Masayuki Ito; Kenichi Nitta; Koji Ohno; Masahito Saigusa; Masaki Nishida; Shinichi Yoshioka; Takahiro Irita; Takao Koike; Tatsuya Kamei; Teruyoshi Komuro; Toshihiro Hattori; Yasuhiro Arai; et al. (IEEE J. Solid State Circuits, 2009)

An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU. - Fumio Arakawa; Takashi Okada; Tomoichi Hayashi; Osamu Nishii; Toshihiro Hattori (Microprocess. Microsystems, 2009)

On coding for nonbinary sources with side information at the decoder. - Shohei Iwata; Toshihiro Hattori; Motohiko Isaka (ISITA, 2010)

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. - Kenichi Iwata; Takahiro Irita; Seiji Mochizuki; Hiroshi Ueda; Masakazu Ehama; Motoki Kimura; Jun Takemura; Keiji Matsumoto; Eiji Yamamoto; Tadashi Teranuma; Katsuji Takakubo; Hiromi Watanabe; et al. (IEEE J. Solid State Circuits, 2010)

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. - Makoto Saen; Kenichi Osada; Yasuyuki Okuma; Kiichi Niitsu; Yasuhisa Shimazaki; Yasufumi Sugimori; Yoshinori Kohama; Kazutaka Kasuga; Itaru Nonomura; Naohiko Irie; Toshihiro Hattori; Atsushi Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

Low-power and high-performance technologies for mobile SoC in LTE era. - Toshihiro Hattori (ISLPED, 2011)

A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor. - Masaki Fujigaya; Noriaki Sakamoto; Takao Koike; Takahiro Irita; Kohei Wakahara; Tsugio Matsuyama; Keiji Hasegawa; Toshiharu Saito; Akira Fukuda; Kaname Teranishi; Kazuki Fukuoka; Noriaki Maeda; et al. (ISSCC, 2013)

Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor. - Kazuki Fukuoka; Noriaki Maeda; Koji Nii; Masaki Fujigaya; Noriaki Sakamoto; Takao Koike; Takahiro Irita; Kohei Wakahara; Tsugio Matsuyama; Keiji Hasegawa; Toshiharu Saito; Akira Fukuda; et al. (IEEE Micro, 2013)

10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores. - Mitsuhiko Igarashi; Toshifumi Uemura; Ryo Mori; Noriaki Maeda; Hiroshi Kishibe; Midori Nagayama; Masaaki Taniguchi; Kohei Wakahara; Toshiharu Saito; Masaki Fujigaya; Kazuki Fukuoka; Koji Nii; et al. (ISSCC, 2014)

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores. - Mitsuhiko Igarashi; Toshifumi Uemura; Ryo Mori; Hiroshi Kishibe; Midori Nagayama; Masaaki Taniguchi; Kohei Wakahara; Toshiharu Saito; Masaki Fujigaya; Kazuki Fukuoka; Koji Nii; Takeshi Kataoka; et al. (IEEE J. Solid State Circuits, 2015)

4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems. - Seiji Mochizuki; Katsushige Matsubara; Keisuke Matsumoto; Chi Lan Phuong Nguyen; Tetsuya Shibayama; Kenichi Iwata; Katsuya Mizumoto; Takahiro Irita; Hirotaka Hara; Toshihiro Hattori (ISSCC, 2016)

A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems. - Seiji Mochizuki; Katsushige Matsubara; Keisuke Matsumoto; Chi Lan Phuong Nguyen; Tetsuya Shibayama; Kenichi Iwata; Katsuya Mizumoto; Takahiro Irita; Hirotaka Hara; Toshihiro Hattori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A 28nm 600MHz Automotive Flash Microcontroller with Virtualization-Assisted Processor for Next-Generation Automotive Architecture Complying with ISO26262 ASIL-D. - Sugako Otani; Norimasa Otsuki; Yasufumi Suzuki; Naoto Okumura; Shohei Maeda; Tomonori Yanagita; Takao Koike; Yasuhisa Shimazaki; Masao Ito; Minoru Uemura; Toshihiro Hattori; Tadaaki Yamauchi; et al. (ISSCC, 2019)

A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D. - Hiroyuki Kondo; Yasuhisa Shimazaki; Masao Ito; Minoru Uemura; Toshihiro Hattori; Noriaki Sakamoto; Sugako Otani; Norimasa Otsuki; Yasufumi Suzuki; Naoto Okumura; Shohei Maeda; Tomonori Yanagita; et al. (IEEE J. Solid State Circuits, 2020)

The 2021 Asia and South Pacific Design Automation Conference (ASPDAC). - Sheldon X.-D. Tan; Toshihiro Hattori (IEEE Des. Test, 2021)

Foreword. - Toshihiro Hattori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)