Highly Efficient String Matching Circuit for IDS with FPGA. - Toshihiro Katashita; Atusi Maeda; Kenji Toda; Yoshinori Yamaguchi (FCCM, 2006)

A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection. - Toshihiro Katashita; Atusi Maeda; Kenji Toda; Yoshinori Yamaguchi (FPL, 2006)

FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet. - Toshihiro Katashita; Yoshinori Yamaguchi; Atusi Maeda; Kenji Toda (IEICE Trans. Inf. Syst., 2007)

Enhanced Correlation Power Analysis Using Key Screening Technique. - Toshihiro Katashita; Akashi Satoh; Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki (ReConFig, 2008)

Development of side-channel attack standard evaluation environment. - Toshihiro Katashita; Akashi Satoh; Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki (ECCTD, 2009)

Hardware Implementations of Hash Function Luffa. - Akashi Satoh; Toshihiro Katashita; Takeshi Sugawara 001; Naofumi Homma; Takafumi Aoki (HOST, 2010)

Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. - Yohei Hori; Takahiro Yoshida; Toshihiro Katashita; Akashi Satoh (ReConFig, 2010)

A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. - Daisuke Fujimoto; Makoto Nagata; Toshihiro Katashita; Akihiro T. Sasaki; Yohei Hori; Akashi Satoh (HOST, 2011)

Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. - Yohei Hori; Hyunho Kang; Toshihiro Katashita; Akashi Satoh (ReConFig, 2011)

Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI. - Takeshi Sugawara 001; Daisuke Suzuki; Toshihiro Katashita (FDTC, 2012)

Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. - Miroslav Knezevic; Kazuyuki Kobayashi; Jun Ikegami; Shin'ichiro Matsuo; Akashi Satoh; Ünal Koçabas; Junfeng Fan; Toshihiro Katashita; Takeshi Sugawara 001; Kazuo Sakiyama; Ingrid Verbauwhede; Kazuo Ohta; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA. - Yohei Hori; Toshihiro Katashita; Kazukuni Kobara (GCCE, 2013)

A novel smart card development platform for evaluating physical attacks and PUFs. - Toshihiro Katashita; Akihiko Sasaki; Yohei Hori (GCCE, 2013)

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. - Daisuke Fujimoto; Toshihiro Katashita; Akihiko Sasaki; Yohei Hori; Akashi Satoh; Makoto Nagata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption. - Yohei Hori; Toshihiro Katashita; Hirofumi Sakane; Kenji Toda; Akashi Satoh (IEICE Trans. Inf. Syst., 2013)

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. - Daisuke Fujimoto; Noriyuki Miura; Makoto Nagata; Yu-ichi Hayashi; Naofumi Homma; Takafumi Aoki; Yohei Hori; Toshihiro Katashita; Kazuo Sakiyama; Thanh-Ha Le; Julien Bringer; Pirouz Bazargan-Sabet; et al. (IEICE Trans. Electron., 2014)

Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. - Yohei Hori; Hyunho Kang; Toshihiro Katashita; Akashi Satoh; Shin-ichi Kawamura; Kazukuni Kobara (J. Inf. Process., 2014)

A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. - Sho Endo; Yang Li 001; Naofumi Homma; Kazuo Sakiyama; Kazuo Ohta; Daisuke Fujimoto; Makoto Nagata; Toshihiro Katashita; Jean-Luc Danger; Takafumi Aoki (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Prototype of USB stick-sized PUF module for authentication and key generation. - Toshihiro Katashita; Yohei Hori; Yasuhiro Ogasahara (GCCE, 2017)

Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. - Toshihiro Katashita; Masakazu Hioki; Yohei Hori; Hanpei Koike (IEICE Trans. Inf. Syst., 2018)

A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-Based Authentication Scheme. - Risa Yashiro; Yohei Hori; Toshihiro Katashita; Kazuo Sakiyama (SECITC, 2019)

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. - Yasuhiro Ogasahara; Yohei Hori; Toshihiro Katashita; Tomoki Iizuka; Hiromitsu Awano; Makoto Ikeda; Hanpei Koike (Integr., 2020)

Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices. - Yusuke Yano; Kengo Iokibe; Toshiaki Teshima; Yoshitaka Toyota; Toshihiro Katashita; Yohei Hori (IEICE Trans. Commun., 2021)

FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. - Tatsuya Oyama; Mika Sakai; Yohei Hori; Toshihiro Katashita; Takeshi Fujino (ACNS Workshops (1), 2024)

Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. - Hiroshi Fuketa; Toshihiro Katashita; Yohei Hori; Masakazu Hioki (IEEE Access, 2024)

Fully Quantized Matrix Arithmetic-Only BERT Model and Its FPGA-Based Accelerator. - Hiroshi Fuketa; Toshihiro Katashita; Yohei Hori; Masakazu Hioki (IEEE Access, 2025)