A 29-ns 64-Mb DRAM with hierarchical array architecture. - Masayuki Nakamura; Tugio Takahashi; Takesada Akiba; Goro Kitsukawa; Makoto Morino; Toshihiro Sekiguchi; Isamu Asano; Katsuo Komatsuzaki; Yoshitaka Tadaki; Songsu Cho; Kazuhiko Kajigaya; Tadashi Tachibana; et al. (IEEE J. Solid State Circuits, 1996)

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. - Tatsuya Matano; Yasuhiro Takai; Tsugio Takahashi; Yuusuke Sakito; Isamu Fujii; Yoshihiro Takaishi; Hiroki Fujisawa; Shuichi Kubouchi; Seiji Narui; Koji Arai; Makoto Morino; Masayuki Nakamura; et al. (IEEE J. Solid State Circuits, 2003)