2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic. - Yasuhiro Takahashi; Youhei Fukuta; Toshikazu Sekine; Michio Yokoyama (APCCAS, 2006)

A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library. - Yasuhiro Takahashi; Toshikazu Sekine; Michio Yokoyama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic. - Yasuhiro Takahashi; Toshikazu Sekine; Michio Yokoyama (IEICE Trans. Electron., 2007)

4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS. - Nazrul Anuar; Yasuhiro Takahashi; Toshikazu Sekine (ECCTD, 2009)

Fundamental logics based on two phase clocked adiabatic static CMOS logic. - Nazrul Anuar; Yasuhiro Takahashi; Toshikazu Sekine (ICECS, 2009)

A new horizontal and vertical common subexpression elimination method for multiple constant multiplication. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (ICECS, 2009)

Two phase clocked adiabatic static CMOS logic. - Nazrul Anuar; Yasuhiro Takahashi; Toshikazu Sekine (SoC, 2009)

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. - Nazrul Anuar; Yasuhiro Takahashi; Toshikazu Sekine (VLSI-SoC, 2010)

Low-power adiabatic SRAM. - Hides Jamima; Yasuhiro Takahashi; Toshikazu Sekine (ISPACS, 2011)

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ISPACS, 2011)

2PCDAL: Two-phase clocking dual-rail adiabatic logic. - Yasuhiro Takahashi; Zhongyu Luo; Toshikazu Sekine; Nazrul Anuar Nayan; Michio Yokoyama (APCCAS, 2012)

A low-power sense amplifier for adiabatic memory using memristor. - Yuki Urata; Yasuhiro Takahashi; Toshikazu Sekine; Nazrul Anuar Nayan (APCCAS, 2012)

Power-saving analysis of adiabatic logic in subthreshold region. - Yasuhiro Takahashi; Toshikazu Sekine; Nazrul Anuar Nayan; Michio Yokoyama (ISPACS, 2012)

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier. - Nazrul Anuar Nayan; Yasuhiro Takahashi; Toshikazu Sekine (Microelectron. J., 2012)

An estimation method for the 3 port S-parameters with 1 port measurements. - Noboru Maeda; Shinji Fukui 002; Toshikazu Sekine; Yasuhiro Takahashi (ECCTD, 2013)

Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ECCTD, 2013)

DPA resistance of charge-sharing symmetric adiabatic logic. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ISCAS, 2013)

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (TSP, 2013)

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (Microelectron. J., 2013)

Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (APCCAS, 2014)

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (APCCAS, 2014)

Power dissipation analysis of memristor for low power integrated circuit applications. - Haruki Ogata; Yasuhiro Takahashi; Toshikazu Sekine (APCCAS, 2014)

Two phase clocking subthreshold adiabatic logic. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (ISCAS, 2014)

An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (ISCAS, 2014)

Process variation verification of low-power secure CSSAL AES S-box circuit. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (MWSCAS, 2014)

An improved estimation method of 4 port S-parameters with 2 port measurements. - Noboru Maeda; Shinji Fukui 002; Toshikazu Sekine; Yasuhiro Takahashi (ECCTD, 2015)

A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (NEWCAS, 2015)

Two phase clocked subthreshold adiabatic logic circuit. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (IEICE Electron. Express, 2015)

SPICE model of memristive device using Tukey window function. - Yasuhiro Takahashi; Toshikazu Sekine; Michio Yokoyama (IEICE Electron. Express, 2015)

Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. - Câncio Monteiro; Yasuhiro Takahashi; Toshikazu Sekine (IET Circuits Devices Syst., 2015)

Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture. - Yuya Kojima; Toshikazu Sekine; Yasuhiro Takahashi (ECCTD, 2017)

Low power Adiabatic Logic based on 2PC2AL. - Mei Han; Yasuhiro Takahashi; Toshikazu Sekine (ICICDT, 2017)

Operational amplifier based LC resonant circuit for adiabatic logic. - Yasuhiro Takahashi; Toshikazu Sekine; Mei Han (MIXDES, 2017)

Non-floating and low-power adiabatic logic circuit. - Mei Han; Yasuhiro Takahashi; Toshikazu Sekine (IEICE Electron. Express, 2019)