A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's. - Hiroyuki Yamauchi; Toshikazu Suzuki; Akihiro Sawada; Tohru Iwata; Toshiaki Tsuji; Masashi Agata; Takashi Taniguchi; Yoshinori Odake; Kazuyuki Sawada; Teruhito Ohnishi; Masanori Fukumoto; Tsutomu Fujita; et al. (IEEE J. Solid State Circuits, 1993)

ATM adaptation layer protocol. - Toshikazu Suzuki (IEEE Commun. Mag., 1994)

Simulating Marbling with Computer Graphics. - Toshikazu Suzuki; Xiaoyang Mao; Atsumi Imamiya (VIIP, 2001)

AtelierM: a physically based interactive system for creating traditional marbling textures. - Xiaoyang Mao; Toshikazu Suzuki; Atsumi Imamiya (GRAPHITE, 2003)

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. - Koji Nii; Yasumasa Tsukamoto; Tomoaki Yoshizawa; Susumu Imaoka; Yoshinobu Yamagami; Toshikazu Suzuki; Akinori Shibayama; Hiroshi Makino; Shuhei Iwade (IEEE J. Solid State Circuits, 2004)

0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier. - Toshikazu Suzuki; Yoshinobu Yamagami; Ichiro Hatanaka; Akinori Shibayama; Hironori Akamatsu; Hiroyuki Yamauchi (IEICE Trans. Electron., 2005)

A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation. - Hiroyuki Yamauchi; Toshikazu Suzuki; Yoshinobu Yamagami (IEICE Trans. Electron., 2006)

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. - Toshikazu Suzuki; Yoshinobu Yamagami; Ichiro Hatanaka; Akinori Shibayama; Hironori Akamatsu; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2006)

A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme. - Toshikazu Suzuki; Hiroyuki Yamauchi; Katsuji Satomi; Hironori Akamatsu (CICC, 2007)

A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses. - Hiroyuki Yamauchi; Toshikazu Suzuki; Yoshinobu Yamagami (IEICE Trans. Electron., 2007)

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses. - Toshikazu Suzuki; Hiroyuki Yamauchi; Yoshinobu Yamagami; Katsuji Satomi; Hironori Akamatsu (IEEE J. Solid State Circuits, 2008)

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. - Toshikazu Suzuki; Shinichi Moriwaki; Atsushi Kawasumi; Shinji Miyano; Hirofumi Shinohara (ESSCIRC, 2010)

Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme. - Atsushi Kawasumi; Toshikazu Suzuki; Shinichi Moriwaki; Shinji Miyano (A-SSCC, 2011)

0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. - Shinichi Moriwaki; Atsushi Kawasumi; Toshikazu Suzuki; Takayasu Sakurai; Shinji Miyano (CICC, 2011)

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. - Yasue Yamamoto; Atsushi Kawasumi; Shinichi Moriwaki; Toshikazu Suzuki; Shinji Miyano; Hirofumi Shinohara (ESSCIRC, 2012)

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. - Shusuke Yoshimoto; Masaharu Terada; Youhei Umeki; Shunsuke Okumura; Atsushi Kawasumi; Toshikazu Suzuki; Shinichi Moriwaki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISLPED, 2012)

A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. - Masaharu Terada; Shusuke Yoshimoto; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ISQED, 2012)

A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy. - Kousuke Miyaji; Toshikazu Suzuki; Shinji Miyano; Ken Takeuchi (ISSCC, 2012)

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. - Shinichi Moriwaki; Yasuhiro Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Shinji Miyano; Takayasu Sakurai; Hirofumi Shinohara (VLSIC, 2012)

A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Electron. Express, 2012)

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IEICE Trans. Electron., 2012)

A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. - Shusuke Yoshimoto; Masaharu Terada; Shunsuke Okumura; Toshikazu Suzuki; Shinji Miyano; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (ASP-DAC, 2013)

Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs. - Yuichi Miyahara; Mitsuhiro Sano; Kazuo Koyama; Toshikazu Suzuki; Koichi Hamashita; Bang-Sup Song (ISSCC, 2013)

A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. - Kousuke Miyaji; Toshikazu Suzuki; Shinji Miyano; Ken Takeuchi (IEEE J. Solid State Circuits, 2013)

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. - Shinji Miyano; Shinichi Moriwaki; Yasue Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Takayasu Sakurai; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2013)

A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity. - Yuichi Miyahara; Mitsuhiro Sano; Kazuo Koyama; Toshikazu Suzuki; Koichi Hamashita; Bang-Sup Song (IEEE J. Solid State Circuits, 2014)