Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus. - Toshimasa Namekawa; Shinji Miyano; Ryo Fukuda; Ryo Haga; Osamu Wada; Hironori Banba; Satoru Takeda; Kazuhiro Suda; Kenichiro Mimoto; Satoshi Yamaguchi; Tsutomu Ohkubo; Hiroshi Takato; et al. (IEEE J. Solid State Circuits, 2000)

Pure CMOS one-time programmable memory using gate-ox anti-fuse. - Hiroshi Ito; Toshimasa Namekawa (CICC, 2004)

Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM. - Osamu Wada; Toshimasa Namekawa; Hiroshi Ito; Atsushi Nakayama; Shuso Fujii (ITC, 2004)