A 32 kbyte integrated cache memory. - Kazuhiro Sawada; Takayasu Sakurai; Kazutaka Nogami; Tsukasa Shirotori; Toshinari Takayanagi; Tetsuya Iizuka; Takeo Maeda; Jinichi Matsunaga; Hiromichi Fuji; Kenji Maeguchi; Kiyoshi Kobayashi; Tomoyuki Ando; et al. (IEEE J. Solid State Circuits, 1989)

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. - Kazutaka Nogami; Takayasu Sakurai; Kazuhiro Sawada; Kenji Sakaue; Yuichi Miyazawa; Shinichi Tanaka; Ypocjo Hiruta; Katsuto Katoh; Toshinari Takayanagi; Tsukasa Shirotori; Yasuo Itoh; Masanori Uchida; et al. (IEEE J. Solid State Circuits, 1990)

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. - Masafumi Takahashi; Tsuyoshi Nishikawa; Mototsugu Hamada; Toshinari Takayanagi; Hideho Arakida; Noriaki Machida; Hideaki Yamamoto; Toshihide Fujiyoshi; Yoko Ohashi; Osamu Yamagishi; Tatsuo Samata; Atsushi Asano; et al. (IEEE J. Solid State Circuits, 2000)

A bitline leakage compensation scheme for low-voltage SRAMs. - Ken-ichi Agawa; Hiroyuki Hara; Toshinari Takayanagi; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2001)

A dual-core 64b ultraSPARC microprocessor for dense server applications. - Toshinari Takayanagi; Jinuk Luke Shin; Bruce Petrick; Jeffrey Y. Su; Ana Sonia Leon (DAC, 2004)

A dual-core 64-bit ultraSPARC microprocessor for dense server applications. - Toshinari Takayanagi; Jinuk Luke Shin; Bruce Petrick; Jeffrey Y. Su; Howard Levy; Ha Pham; Jinseung Son; Nathan Moon; Dina Bistry; Umesh Nair; Mandeep Singh; Vikas Mathur; et al. (IEEE J. Solid State Circuits, 2005)

Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC. - Vincent von Kaenel; Toshinari Takayanagi (CICC, 2007)

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems. - Zongjian Chen; Priya Ananthanarayanan; Sukalp Biswas; Brian Campbell 004; Hao Chen; Shaishav Desai; Dominic Go; Rajat Goel; Vincent von Kaenel; Jason Kassoff; Fabian Klass; Weichun Ku; et al. (ISSCC, 2007)