Word-parallel coprocessor architecture for digital nearest Euclidean distance search. - Toshinobu Akazawa; Seiryu Sasaki; Hans Jürgen Mattausch (ESSCIRC, 2013)

LVQ neural network SoC adaptable to different on-chip learning and recognition applications. - Fengwei An; Toshinobu Akazawa; Shogo Yamazaki; Lei Chen 001; Hans Jürgen Mattausch (APCCAS, 2014)

A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability. - Fengwei An; Toshinobu Akazawa; Shogo Yamazaki; Lei Chen 001; Hans Jürgen Mattausch (CICC, 2014)

k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching. - Fengwei An; Lei Chen 001; Toshinobu Akazawa; Shogo Yamazaki; Hans Jürgen Mattausch (IEICE Trans. Electron., 2016)