A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal States. - Toshinobu Ono; Masaaki Yoshida (ITC, 1991)

Selecting partial scan flip-flops for circuit partitioning. - Toshinobu Ono (ICCAD, 1994)

Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs. - Toshinobu Ono; Kazuo Wakui; Hitoshi Hikima; Yoshiyuki Nakamura; Masaaki Yoshida (Asian Test Symposium, 1997)

An Application of Partial Scan Techniques to a High-End System LSI Design. - Toshinobu Ono; Akira Kozawa; Takashi Kimura; Yoshihiro Konno; Koji Saga (Asian Test Symposium, 2001)