A State Traversal Algorithm Using a State Covariance Matrix. - Akira Motohara; Toshinori Hosokawa; Michiaki Muraoka; Hidetsugu Maekawa; Kazuhiro Kayashima; Yasuharu Shimeki; Seichi Shin (DAC, 1993)

Design for testability using register-transfer level partial scan selection. - Akira Motohara; Sadami Takeoka; Toshinori Hosokawa; Mitsuyasu Ohta; Yuji Takai; Michihiro Matsumoto; Michiaki Muraoka (ASP-DAC, 1995)

A Design for testability Method Using RTL Partitioning. - Toshinori Hosokawa; Kenichi Kawaguchi; Mitsuyasu Ohta; Michiaki Muraoka (Asian Test Symposium, 1996)

A Partial Scan Design Method Based on n-Fold Line-up Structures. - Toshinori Hosokawa; Toshihiro Hiraoka; Mitsuyasu Ohta; Michiaki Muraoka; Shigeo Kuninobu (Asian Test Symposium, 1997)

An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. - Tomoo Inoue; Toshinori Hosokawa; Takahiro Mihara; Hideo Fujiwara (Asian Test Symposium, 1998)

Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. - Toshinori Hosokawa; Toshihiro Hiraoka; Tomoo Inoue; Hideo Fujiwara (Asian Test Symposium, 1999)

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. - Toshinori Hosokawa; Masayoshi Yoshimura; Mitsuyasu Ohta (ASP-DAC, 2001)

A SoC Test Strategy Based on a Non-Scan DFT Method. - Hiroshi Date; Toshinori Hosokawa; Michiaki Muraoka (Asian Test Symposium, 2002)

A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. - Toshinori Hosokawa; Hiroshi Date; Michiaki Muraoka (Asian Test Symposium, 2002)

A Test Point Insertion Method to Reduce the Number of Test Patterns. - Masayoshi Yoshimura; Toshinori Hosokawa; Mitsuyasu Ohta (Asian Test Symposium, 2002)

A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. - Toshinori Hosokawa; Hiroshi Date; Michiaki Muraoka (VTS, 2002)

Test sequence compaction methods for acyclic sequential circuits using a time expansion model. - Toshinori Hosokawa; Tomoo Inoue; Toshihiro Hiraoka; Hideo Fujiwara (Syst. Comput. Jpn., 2002)

VCore-based design methodology. - Michiaki Muraoka; Hideyuki Hamada; Hiroaki Nishi; Toshihiko Tada; Yoichi Onishi; Toshinori Hosokawa; Kenji Yoshida (ASP-DAC, 2003)

A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. - Toshinori Hosokawa; Hiroshi Date; Masahide Miyazaki; Michiaki Muraoka; Hideo Fujiwara (Asian Test Symposium, 2003)

A DFT Selection Method for Reducing Test Application Time of System-on-Chips. - Masahide Miyazaki; Toshinori Hosokawa; Hiroshi Date; Michiaki Muraoka; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2004)

An Effective Design for Hierarchical Test Generation Based on Strong Testability. - Hideyuki Ichihara; Tomoo Inoue; Naoki Okamoto; Toshinori Hosokawa; Hideo Fujiwara (Asian Test Symposium, 2005)

Fault-dependent/independent Test Generation Methods for State Observable FSMs. - Toshinori Hosokawa; Ryoichi Inoue; Hideo Fujiwara (ATS, 2007)

A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. - Ryoichi Inoue; Toshinori Hosokawa; Hideo Fujiwara (ATS, 2008)

Evaluation of transition untestable faults using a multi-cycle capture test generation method. - Masayoshi Yoshimura; Hiroshi Ogawa; Toshinori Hosokawa; Koji Yamazaki (DDECS, 2010)

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. - Ryoichi Inoue; Toshinori Hosokawa; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2010)

A don't care identification method for test compaction. - Hiroshi Yamazaki; Motohiro Wakazono; Toshinori Hosokawa; Masayoshi Yoshimura (DDECS, 2013)

A smart Trojan circuit and smart attack method in AES encryption circuits. - Masayoshi Yoshimura; Amy Ogita; Toshinori Hosokawa (DFTS, 2013)

A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution. - Hiroshi Yamazaki; Motohiro Wakazono; Toshinori Hosokawa; Masayoshi Yoshimura (IEICE Trans. Inf. Syst., 2013)

A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation. - Tetsuya Masuda; Jun Nishimaki; Toshinori Hosokawa; Hideo Fujiwara (ATS, 2015)

A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions. - Masayoshi Yoshimura; Yoshiyasu Takahashi; Hiroshi Yamazaki; Toshinori Hosokawa (ATS, 2015)

A low capture power test generation method using capture safe test vectors. - Atsushi Hirai; Yukari Yamauchi; Toshinori Hosokawa; Masayuki Arai (ETS, 2015)

A scheduling method for hierarchical testability based on test environment generation results. - Jun Nishimaki; Toshinori Hosokawa; Hideo Fujiwara (ETS, 2016)

A dynamic test compaction method on low power test generation based on capture safe test vectors. - Toshinori Hosokawa; Atsushi Hirai; Hiroshi Yamazaki; Masayuki Arai (DFT, 2017)

Controller augmentation and test point insertion at RTL for concurrent operational unit testing. - Toshinori Hosokawa; Shun Takeda; Hiroshi Yamazaki; Masayoshi Yoshimura (IOLTS, 2017)

A Diagnostic Fault Simulation Method for a Single Universal Logical Fault Model. - Toshinori Hosokawa; Hideyuki Takano; Hiroshi Yamazaki; Koji Yamazaki (PRDC, 2017)

A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations. - Masayoshi Yoshimura; Tomohiro Bouyashiki; Toshinori Hosokawa (PRDC, 2017)

A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation. - Toshinori Hosokawa; Atsushi Hirai; Yukari Yamauchi; Masayuki Arai (IEICE Trans. Inf. Syst., 2017)

A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT. - Masayoshi Yoshimura; Yoshiyasu Takahashi; Hiroshi Yamazaki; Toshinori Hosokawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification. - Toshinori Hosokawa; Morito Niseki; Masayoshi Yoshimura; Hiroshi Yamazaki; Masayuki Arai; Hiroyuki Yotsuyanagi; Masaki Hashizume (IOLTS, 2018)

A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns. - Toshinori Hosokawa; Hiroshi Yamazaki; Shun Takeda; Masayoshi Yoshimura (IOLTS, 2018)

A Capture Safe Static Test Compaction Method Based on Don't Cares. - Sayuri Ochi; Hiroshi Yamazaki; Toshinori Hosokawa; Masayoshi Yoshimura (IOLTS, 2018)

A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively. - Toshinori Hosokawa; Hiroshi Yamazaki; Kenichiro Misawa; Masayoshi Yoshimura; Yuki Hirama; Masavuki Arai (DFT, 2019)

A State Assignment Method to Improve Transition Fault Coverage for Controllers. - Masayoshi Yoshimura; Yuki Takeuchi; Hiroshi Yamazaki; Toshinori Hosokawa (DFT, 2019)

A Design for Testability Method for k-Cycle Capture Test Generation. - Yuta Ishiyama; Toshinori Hosokawa; Hiroshi Yamazaki (IOLTS, 2019)

A Test Generation Method Based on k-Cycle Testing for Finite State Machines. - Yuya Kinoshita; Toshinori Hosokawa; Hideo Fujiwara (IOLTS, 2019)

A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths. - Yuki Takeuchi; Toshinori Hosokawa; Hiroshi Yamazaki; Masayoshi Yoshimura (IOLTS, 2019)

A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT. - Ryuki Asami; Toshinori Hosokawa; Masayoshi Yoshimura; Masayuki Arai (DFT, 2020)

A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method. - Toshinori Hosokawa; Kenichiro Misawa; Hiroshi Yamazaki; Masayoshi Yoshimura; Masayuki Arai (IOLTS, 2020)

A Test Sensitization State Compaction Method on Controller Augmentation. - Yuki Ikegaya; Toshinori Hosokawa; Yuta Ishiyama; Hiroshi Yamazaki (IOLTS, 2020)

Universal Testing for Linear Feed-Forward/Feedback Shift Registers. - Hideo Fujiwara; Katsuya Fujiwara; Toshinori Hosokawa (IEICE Trans. Inf. Syst., 2020)

CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level. - Masayoshi Yoshimura; Atsuya Tsujikawa; Hiroshi Yamazaki; Toshinori Hosokawa (DFT, 2022)

An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers. - Toshinori Hosokawa; Kyohei Iizuka; Masayoshi Yoshimura (DFT, 2023)

A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage. - Momona Mizota; Toshinori Hosokawa; Masayoshi Yoshimura; Masayuki Arai (DFT, 2023)

An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information. - Natsuki Ota; Toshinori Hosokawa; Koji Yamazaki; Yukari Yamauchi; Masayuki Arai (DFT, 2023)

An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing. - Yudai Toyooka; Haruki Watanabe; Toshinori Hosokawa; Masayoshi Yoshimura (DFT, 2023)

A Low Power Oriented Multiple Target Test Generation Method for 2-Cycle Gate-Exhaustive Faults. - Toshinori Hosokawa; Momona Mizota; Masayoshi Yoshimura; Masayuki Arai (DFT, 2024)

CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level. - Masayoshi Yoshimura; Atsuya Tsujikawa; Toshinori Hosokawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)