Hierarchical routing bus. - Toshinori Sueyoshi (Syst. Comput. Jpn., 1985)

Performance evaluation of the binary tree access mechanism in mimd type parallel computers. - Toshinori Sueyoshi; Keizo Saisho; Itsujiro Arita (Syst. Comput. Jpn., 1986)

An overview of the Kyushu University reconfigurable parallel processor. - Kazuaki J. Murakami; Akira Fukuda; Toshinori Sueyoshi; Shinji Tomita (SIGARCH Comput. Archit. News, 1988)

The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures. - Kazuaki J. Murakami; Shin-ichiro Mori; Akira Fukuda; Toshinori Sueyoshi; Shinji Tomita (ICS, 1989)

The Kyushu University Reconfigurable Parallel Processor - Design Philosophy and Architecture. - Kazuaki J. Murakami; Shin-ichiro Mori; Akira Fukuda; Toshinori Sueyoshi; Shinji Tomita (IFIP Congress, 1989)

Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. - Yulu Yang; Hideharu Amano; Hidetomo Shibamura; Toshinori Sueyoshi (SPDP, 1993)

Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. - Kei Hiraki; Hideharu Amano; Morihiro Kuga; Toshinori Sueyoshi; Tomohiro Kudoh; Hiroshi Nakashima; Hironori Nakajo; Hideo Matsuda; Takashi Matsumoto 002; Shin-ichiro Mori (ISPAN, 1994)

Recursive Diagonal Torus (RDT): An Interconnection Network for the Massively Parallel Computers. - Yulu Yang; Hideharu Amano; Hidetomo Shibamura; Toshinori Sueyoshi (Syst. Comput. Jpn., 1996)

Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. - Yulu Yang; Akira Funahashi; Akiya Jouraku; Hiroaki Nishi; Hideharu Amano; Toshinori Sueyoshi (IEEE Trans. Parallel Distributed Syst., 2001)

Configurable and Reconfigurable Computing for Digital Signal Processing. - Toshinori Sueyoshi; Masahiro Iida (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

KITE microprocessor and CAE for computer science. - Toshinori Sueyoshi; Morihiro Kuga; Hidetomo Shibamura (Syst. Comput. Jpn., 2002)

EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA. - Hidetomo Shibamura; Masayuki Fukuyama; Daisuke Uchida; Seiji Ikeda; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2004)

Foreword. - Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2004)

Applying the Small-World Network to Routing Structure of FPGAs. - Hisashi Tsukiashi; Masahiro Iida; Toshinori Sueyoshi (FPL, 2005)

Effective clustering technique to optimize routability of outer cluster nets. - Masaki Kobata; Masahiro Iida; Toshinori Sueyoshi (FPGA, 2006)

Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device. - Motoki Amagasaki; Takurou Shimokawa; Kazunori Matsuyama; Ryoichi Yamaguchi; Hideaki Nakayama; Naoto Hamabe; Masahiro Iida; Toshinori Sueyoshi (VLSI-SoC, 2006)

Self-Similar Property for TCP Traffic under the Bottleneck Restrainment. - Takuo Nakashima; Toshinori Sueyoshi (AINA Workshops (1), 2007)

Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping. - Kazunori Matsuyama; Motoki Amagasaki; Hideaki Nakayama; Ryoichi Yamaguchi; Masahiro Iida; Toshinori Sueyoshi (ARC, 2007)

Performance Estimation of TCP under SYN Flood Attacks. - Takuo Nakashima; Toshinori Sueyoshi (CISIS, 2007)

A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic. - Hiroshi Shinohara; Hideaki Monji; Masahiro Iida; Toshinori Sueyoshi (FCCM, 2007)

A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores. - Motoki Amagasaki; Ryoichi Yamaguchi; Kazunori Matsuyama; Masahiro Iida; Toshinori Sueyoshi (FPL, 2007)

An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell Architecture. - Yoshiaki Satou; Motoki Amagasaki; Hiroshi Miura; Kazunori Matsuyama; Ryoichi Yamaguchi; Masahiro Iida; Toshinori Sueyoshi (FPT, 2007)

Queueing Analysis for Self-similar Traffic by Simulator. - Takuo Nakashima; Akari Ono; Toshinori Sueyoshi (IIH-MSP, 2007)

A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices. - Hiroshi Shinohara; Hideaki Monji; Masahiro Iida; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2007)

Special Section on Reconfigurable Systems. - Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2007)

Analysis of Queueing Property for Self-Similar Traffic. - Takuo Nakashima; Toshinori Sueyoshi (AINA, 2008)

Extraction of Characteristics of Anomaly Accessed IP Packets by the Entropy-Based Analysis. - Takuo Nakashima; Shunsuke Oshima; Yusuke Nishikido; Toshinori Sueyoshi (CISIS, 2008)

Performance Framework for P2P Overlay Network. - Takuo Nakashima; Akari Ono; Toshinori Sueyoshi (IIH-MSP, 2008)

Queueing Property for Different Type of Self-Similar Traffics. - Takuo Nakashima; Yusuke Shomura; Toshinori Sueyoshi (IIH-MSP, 2008)

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture. - Motoki Amagasaki; Ryoichi Yamaguchi; Masahiro Koga; Masahiro Iida; Toshinori Sueyoshi (Int. J. Reconfigurable Comput., 2008)

Memory Sharing Approach for TMR Softcore Processor. - Yoshihiro Ichinomiya; Shiro Tanoue; Tomoyuki Ishida; Motoki Amagasaki; Morihiro Kuga; Toshinori Sueyoshi (ARC, 2009)

A Novel Local Interconnect Architecture for Variable Grain Logic Cell. - Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (ARC, 2009)

A novel states recovery technique for the TMR softcore processor. - Shiro Tanoue; Tomoyuki Ishida; Yoshihiro Ichinomiya; Motoki Amagasaki; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2009)

DoS/DDoS Detection Scheme Using Statistical Method Based on the Destination Port Number. - Shunsuke Oshima; Arata Hirakawa; Takuo Nakashima; Toshinori Sueyoshi (IIH-MSP, 2009)

Improvement of Execution Efficiency on the MX Core. - Mitsutaka Nakano; Masahiro Iida; Toshinori Sueyoshi (PDCAT, 2009)

DDoS Detection Technique Using Statistical Analysis to Generate Quick Response Time. - Shunsuke Oshima; Takuo Nakashima; Toshinori Sueyoshi (BWCCA, 2010)

Early DoS/DDoS Detection Method using Short-term Statistics. - Shunsuke Oshima; Takuo Nakashima; Toshinori Sueyoshi (CISIS, 2010)

Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration. - Yoshihiro Ichinomiya; Shiro Tanoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FCCM, 2010)

First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. - Masahiro Koga; Masahiro Iida; Motoki Amagasaki; Yoshinobu Ichida; Mitsuro Saji; Jun Iida; Toshinori Sueyoshi (FPL, 2010)

COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area Minimization. - Yasuhiro Okamoto; Yoshihiro Ichinomiya; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (FPL, 2010)

A robust reconfigurable logic device based on less configuration memory logic cell. - Qian Zhao 001; Yoshihiro Ichinomiya; Yasuhiro Okamoto; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (FPT, 2010)

Power-aware FPGA routing fabrics and design tools. - Shoichi Nishida; Jyunya Eto; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2010)

A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. - Kazuki Inoue; Qian Zhao 001; Yasuhiro Okamoto; Hiroki Yosho; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (ACM Trans. Reconfigurable Technol. Syst., 2010)

A novel reconfigurable logic device base on 3D stack technology. - Qian Zhao 001; Yusuke Iwai; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (3DIC, 2011)

Anomaly Detection Using Chi-square Values Based on the Typical Features and the Time Deviation. - Shunsuke Oshima; Takuo Nakashima; Toshinori Sueyoshi (AINA, 2011)

An Anomaly Detection System Based on Chi-Square Method with Dynamic BIN Algorithm. - Shunsuke Oshima; Yusuke Ichimura; Takuo Nakashima; Toshinori Sueyoshi (BWCCA, 2011)

An Easily Testable Routing Architecture and Efficient Test Technique. - Kazuki Inoue; Hiroki Yosho; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (FPL, 2011)

Comparison of Properties between Entropy and Chi-Square Based Anomaly Detection Method. - Shunsuke Oshima; Takuo Nakashima; Toshinori Sueyoshi (NBiS, 2011)

An easily testable routing architecture of FPGA. - Masahiro Iida; Kazuki Inoue; Motoki Amagasaki; Toshinori Sueyoshi (VLSI-SoC, 2011)

A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. - Qian Zhao 001; Yoshihiro Ichinomiya; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (IEEE Embed. Syst. Lett., 2011)

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. - Masahiro Iida; Masahiro Koga; Kazuki Inoue; Motoki Amagasaki; Yoshinobu Ichida; Mitsuro Saji; Jun Iida; Toshinori Sueyoshi (IEICE Trans. Electron., 2011)

Improving the Soft-error Tolerability of a Soft-core Processor on. - Yoshihiro Ichinomiya; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (J. Next Gener. Inf. Technol., 2011)

Parallelization of the channel width search for FPGA routing. - Hiroomi Sawada; Morihiro Kuga; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (SIGARCH Comput. Archit. News, 2011)

The Evaluation of an Anomaly Detection System Based on Chi-square Method. - Shunsuke Oshima; Takuo Nakashima; Toshinori Sueyoshi (AINA Workshops, 2012)

Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams. - Yoshihiro Ichinomiya; Sadaki Usagawa; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FCCM, 2012)

Fault detection and avoidance of FPGA in various granularities. - Kazuki Inoue; Yuki Nishitani; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2012)

Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. - Yoshihiro Ichinomiya; Kohei Takano; Motoki Amagasaki; Morihiro Kuga; Masahiro Iida; Toshinori Sueyoshi (FPT, 2012)

Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration. - Makoto Fujino; Hiroki Tanaka; Yoshihiro Ichinomiya; Motoki Amagasaki; Morihiro Kuga; Masahiro Iida; Toshinori Sueyoshi (ICA3PP (1), 2012)

A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration. - Yoshihiro Ichinomiya; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ICA3PP (1), 2012)

A novel physical defects recovery technique for FPGA-IP cores. - Yuki Nishitani; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ReConFig, 2012)

Evaluation of fault tolerant technique based on homogeneous FPGA architecture. - Yuki Nishitani; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2012)

Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration. - Yoshihiro Ichinomiya; Tsuyoshi Kimura; Motoki Amagasaki; Morihiro Kuga; Masahiro Iida; Toshinori Sueyoshi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. - Masahiro Iida; Motoki Amagasaki; Yasuhiro Okamoto; Qian Zhao 001; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2012)

An Easily Testable Routing Architecture and Prototype Chip. - Kazuki Inoue; Masahiro Koga; Motoki Amagasaki; Masahiro Iida; Yoshinobu Ichida; Mitsuro Saji; Jun Iida; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2012)

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). - Qian Zhao 001; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPGA, 2013)

Defect-robust FPGA architectures for intellectual property cores in system LSI. - Motoki Amagasaki; Kazuki Inoue; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2013)

An automatic FPGA design and implementation framework. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2013)

An FPGA design and implementation framework combined with commercial VLSI CADs. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ReCoSoC, 2013)

Three-dimensional stacking FPGA architecture using face-to-face integration. - Tetsuro Hamada; Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2013)

FPGA Design Framework Combined with Commercial VLSI CAD. - Qian Zhao 001; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2013)

A reconfigurable Java accelerator with software compatibility for embedded systems. - Yuki Ogawa; Masahiro Iida; Motoki Amagasaki; Morihiro Kuga; Toshinori Sueyoshi (SIGARCH Comput. Archit. News, 2013)

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. - Qian Zhao 001; Kyosei Yanagida; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2014)

A novel three-dimensional FPGA architecture with high-speed serial communication links. - Takuya Kajiwara; Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morituro Kuga; Toshinori Sueyoshi (FPT, 2014)

Zyndroid: An Android platform for software/hardware coprocessing. - Susumu Mashimo; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2014)

Blokus Duo engine on a Zynq. - Susumu Mashimo; Kansuke Fukuda; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2014)

Simple wafer stacking 3D-FPGA architecture. - Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ICICDT, 2015)

Architecture exploration of 3D FPGA to minimize internal layer connection. - Motoki Amagasaki; Yuto Takeuchi; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2015)

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. - Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2015)

A 3D FPGA Architecture to Realize Simple Die Stacking. - Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

hCODE: An open-source platform for FPGA accelerators. - Qian Zhao 001; Takuya Nakamichi; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2016)

An area compact soft error resident circuit for FPGA. - Motoki Amagasaki; Yuji Nakamura; Takuya Teraoka; Masahiro Iida; Toshinori Sueyoshi (ICICDT, 2016)

A novel soft error tolerant FPGA architecture. - Motoki Amagasaki; Yuji Nakamura; Takuya Teraoka; Masahiro Iida; Toshinori Sueyoshi (VLSI-SoC, 2016)

SLM: A Scalable Logic Module Architecture with Less Configuration Memory. - Motoki Amagasaki; Ryo Araki; Masahiro Iida; Toshinori Sueyoshi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Study of Heterogeneous Computing Design Method based on Virtualization Technology. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (SIGARCH Comput. Archit. News, 2016)

A Study of FPGA Virtualization and Accelerator Scheduling. - Qian Zhao 001; Masahiro Iida; Toshinori Sueyoshi (ETCD@ASPLOS, 2017)

hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. - Qian Zhao 001; Hendarmawan; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2017)

FPGA based ASIC Emulator with High Speed Optical Serial Links. - Motoki Amagasaki; Futoshi Murase; Morihiro Kuga; Masahiro Iida; Toshinori Sueyoshi (HEART, 2017)

High-level Synthesis based on Parallel Design Patterns using a Functional Language. - Morihiro Kuga; Kansuke Fukuda; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (HEART, 2017)

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. - Motoki Amagasaki; Yuki Nishitani; Kazuki Inoue; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2017)

Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IPSJ Trans. Syst. LSI Des. Methodol., 2017)

Basic Knowledge to Understand FPGAs. - Toshinori Sueyoshi (Principles and Structures of FPGAs, 2018)

Three Dimensional FPGA Architecture with Fewer TSVs. - Motoki Amagasaki; Masato Ikebe; Qian Zhao 001; Masahiro Iida; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2018)

Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2018)