One-dimensional logic gate assignment and interval graphs. - Tatsuo Ohtsuki; Hajimu Mori; Ernest S. Kuh; Toshinobu Kashiwabara; Toshio Fujisawa (COMPSAC, 1979)

On Minimal Augmentation of a Graph to Obtain an Interval Graph. - Tatsuo Ohtsuki; Hajimu Mori; Toshinobu Kashiwabara; Toshio Fujisawa (J. Comput. Syst. Sci., 1981)

Efficient algorithms for finding maximum cliques of an overlap graph. - Sumio Masuda; Kazuo Nakajima; Toshinobu Kashiwabara; Toshio Fujisawa (Networks, 1990)

Crossing Minimization in Linear Embeddings of Graphs. - Sumio Masuda; Kazuo Nakajima; Toshinobu Kashiwabara; Toshio Fujisawa (IEEE Trans. Computers, 1990)

Polynomial time algorithms on circular-arc overlap graphs. - Toshinobu Kashiwabara; Sumio Masuda; Kazuo Nakajima; Toshio Fujisawa (Networks, 1991)

Generation of Maximum Independent Sets of a Bipartite Graph and Maximum Cliques of a Circular-Arc Graph. - Toshinobu Kashiwabara; Sumio Masuda; Kazuo Nakajima; Toshio Fujisawa (J. Algorithms, 1992)

A single-chip 802.11a MAC/PHY with a 32-b RISC processor. - Toshio Fujisawa; Jun Hasegawa; Koji Tsuchie; Tatsuo Shiozawa; Tetsuya Fujita; Toshitada Saito; Yasuo Unekawa (IEEE J. Solid State Circuits, 2003)

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. - Daisuke Taki; Tatsuo Shiozawa; Kuniaki Ito; Youichiro Shiba; Kouji Horisaki; Hirotsugu Kajihara; Toshiyuki Yamagishi; Masahiro Sekiya; Akira Yamaga; Tetsuya Fujita; Hiroyuki Hara; Masanori Kuwahara; et al. (COOL Chips, 2011)

A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor. - Hideki Yamada; Toshiyuki Yamagishi; Tomoya Suzuki; Kuniaki Ito; Koji Horisaki; Tom Vander Aa; Toshio Fujisawa; Liesbet Van der Perre; Yasuo Unekawa (COOL Chips, 2011)

High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors. - Tomoya Suzuki; Hideki Yamada; Toshiyuki Yamagishi; Daisuke Takeda; Koji Horisaki; Tom Vander Aa; Toshio Fujisawa; Liesbet Van der Perre; Yasuo Unekawa (IEEE Micro, 2011)

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension. - Konosuke Watanabe; Kenichiro Yoshii; Nobuhiro Kondo; Ken-ichi Maeda; Toshio Fujisawa; Junji Wadatsumi; Daisuke Miyashita; Shouhei Kousai; Yasuo Unekawa; Shinsuke Fujii; Takuma Aoyama; Takayuki Tamura; et al. (ISSCC, 2014)

Bringing in Cryogenics to Storage: Characteristics and Performance Improvement of 3D Flash Memory. - Yuta Aiba; Hitomi Tanaka; Takashi Maeda; Keiichi Sawa; Fumie Kikushima; Masayuki Miura; Toshio Fujisawa; Mie Matsuo; Hideto Horii; Hideko Mukaida; Tomoya Sanuki (IMW, 2021)

Demonstration of Recovery Annealing on 7-Bits per Cell 3D Flash Memory at Cryogenic Operation for Bit Cost Scalability and Sustainability. - Yuta Aiba; Yusuke Higashi; Hitomi Tanaka; Hiroki Tanaka; Fumie Kikushima; Toshio Fujisawa; Hideko Mukaida; Masayuki Miura; Tomoya Sanuki (VLSI Technology and Circuits, 2023)