A large scale cellular array processor: AAP-1. - Toshio Kondo; Tayoshi Nakashima; Toshio Tsuchiya; Yoshi Sugiyama; Tsuneta Sudo (ACM Conference on Computer Science, 1985)

Automatic position findings of vehicle by means of laser. - Kenichi Nishide; Moritomo Hanawa; Toshio Kondo (ICRA, 1986)

Pseudo MIMD Array Processor - AAP2. - Toshio Kondo; Toshio Tsuchiya; Yoshihiro Kitamura; Yoshi Sugiyama; Takashi Kimura; Takayoshi Nakashima (ISCA, 1986)

Two-Dimensional Array Processor AAP2 and Its Programming Language. - Toshio Kondo; Yoshi Sugiyama; Takayoshi Nakashima (Syst. Comput. Jpn., 1989)

A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding. - Kazuhito Suguri; Toshihiro Minami; Hiroaki Matsuda; Ritsu Kusaba; Toshio Kondo; Ryota Kasai; Takumi Watanabe; Hidenuri Sato; Nobutarou Shibata; Yutaka Tashiro; Takaaki Izuoka; Atsushi Shimizu; et al. (IEEE J. Solid State Circuits, 1996)

Two-chip MPEG-2 video encoder. - Toshio Kondo; Kazuhito Suguri; Mitsuo Ikeda; Tetsuya Abe; Hiroaki Matsuda; Tsuneo Okubo; Kenji Ogura; Yutaka Tashiro; Naoki Ono; Toshihiro Minami; Ritsu Kusaba; Takeshi Ikenaga; et al. (IEEE Micro, 1996)

An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. - Mitsuo Ikeda; Toshio Kondo; Koyo Nitta; Kazuhito Suguri; Takeshi Yoshitome; Toshihiro Minami; Jiro Naganuma; Takeshi Ogura (DATE, 1999)

SuperENC: MPEG-2 video encoder chip. - Mitsuo Ikeda; Toshio Kondo; Koyo Nitta; Kazuhito Suguri; Takeshi Yoshitome; Toshihiro Minami; Hiroe Iwasaki; Katsuyuki Ochiai; Jiro Naganuma; Makoto Endo; Yutaka Tashiro; Hiroshi Watanabe 005; et al. (IEEE Micro, 1999)

Concurrent and collaborative methodologies in short TAT LSI design and manufacturing. - Tsuneo Okubo; Mitsuo Ikeda; Yutaka Tashiro; Toshio Kondo; Ryota Kasai; Hiroshi Kotera; Tetsuma Sakurai (Syst. Comput. Jpn., 1999)

Low-power motion-estimation architecture based on a novel early-jump-out technique. - Wujian Zhang; Runde Zhou; Toshio Kondo (ISCAS (5), 2001)

Evaluation of low-energy and high-performance processor using variable stages pipeline technique. - Takahiro Sasaki; Yuji Ichikawa; Tetsuo Hironaka; Toshiaki Kitamura; Toshio Kondo (IET Comput. Digit. Tech., 2008)

Evaluation of Variable Level Cache. - Nobuyuki Matsubara; Takahiro Sasaki; Kazuhiko Ohno; Toshio Kondo (ISIA, 2010)

Design and evaluation of variable stages pipeline processor chip. - Tomoyuki Nakabayashi; Takahiro Sasaki; Kazuhiko Ohno; Toshio Kondo (ASP-DAC, 2011)

Low power semi-static TSPC D-FFs using split-output latch. - Tomoyuki Nakabayashi; Takahiro Sasaki; Kazuhiko Ohno; Toshio Kondo (ISOCC, 2011)

Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture. - Tomoyuki Nakabayashi; Takahiro Sasaki; Kazuhiko Ohno; Toshio Kondo (ICNC, 2012)

Design and evaluation of variable stages pipeline processor with low-energy techniques. - Tomoyuki Nakabayashi; Takahiro Sasaki; I. K. Ohno; Toshio Kondo (IET Comput. Digit. Tech., 2012)

Dynamic BTB Resizing for Variable Stages Superscalar Architecture. - Tomoyuki Nakabayashi; Takahiro Sasaki; Toshio Kondo (CANDAR, 2013)

FabCache: Cache Design Automation for Heterogeneous Multi-core Processors. - Takaki Okamoto; Tomoyuki Nakabayashi; Takahiro Sasaki; Toshio Kondo (CANDAR, 2013)

Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor. - Takahiro Sasaki; Tomoyuki Nakabayashi; Kazumasa Nomura; Kazuhiko Ohno; Toshio Kondo (IET Comput. Digit. Tech., 2013)

Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip. - Tomoyuki Nakabayashi; Takahiro Sasaki; Hitoshi Nakamura; Kazuhiko Ohno; Toshio Kondo (Int. J. Netw. Comput., 2013)

Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. - Tomoyuki Nakabayashi; Tomoyuki Sugiyama; Takahiro Sasaki; Eric Rotenberg; Toshio Kondo (ASP-DAC, 2014)

Detail Design and Evaluation of Fab Cache. - Takaki Okamoto; Tomoyuki Nakabayashi; Takahiro Sasaki; Toshio Kondo (CANDAR, 2014)

Register Port Prediction for a Banked Register File. - Hiroaki Kawashima; Takahiro Sasaki; Yuki Fukazawa; Toshio Kondo (CANDAR, 2015)

An Architectural Framework of Snoopy Interconnection for Heterogeneous Cache Systems. - Seiji Miyoshi; Takahiro Sasaki; Yuki Fukazawa; Toshio Kondo (CANDAR, 2015)

A cache memory with unit tile and line accessibility. - BaoKang Wang; Yuki Fukazawa; Toshio Kondo; Takahiro Sasaki (ICIS, 2016)

A Rapid Verification Framework for Developing Multi-core Processor. - Kouki Kayamuro; Takahiro Sasaki; Yuki Fukazawa; Toshio Kondo (CANDAR, 2016)

SIMD-based datapath with efficient operation structure for motion estimation. - Yuki Fukazawa; Keita Watanabe; Yuki Minoura; Toshio Kondo; Takahiro Sasaki (ICASSP, 2016)

Tile/line access cache memory based on a multi-level Z-order tiling data layout. - BaoKang Wang; Yuki Fukazawa; Toshio Kondo; Takahiro Sasaki (Concurr. Comput. Pract. Exp., 2018)