A Control Mechanism of a Lisp-Based Data-Driven Machine. - Toshitsugu Yuba; Yoshinori Yamaguchi; Toshio Shimada (Inf. Process. Lett., 1983)

An Architecture of a Data Flow Machine and Its Evaluation. - Toshio Shimada; Kei Hiraki; Kenji Nishida (COMPCON, 1984)

Evaluation of Associative Memory Using Parallel Chained Hashing. - Kei Hiraki; Kenji Nishida; Toshio Shimada (IEEE Trans. Computers, 1984)

Maintenance Architecture and Its LSI Implementation of a Dataflow Computer with a Large Number of Processors. - Kei Hiraki; Kenji Nishida; Satoshi Sekiguchi; Toshio Shimada (ICPP, 1986)

Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations. - Toshio Shimada; Kei Hiraki; Kenji Nishida; Satoshi Sekiguchi (ISCA, 1986)

The SIGMA-1 dataflow computer. - Toshitsugu Yuba; Kei Hiraki; Toshio Shimada; Satoshi Sekiguchi; Kenji Nishida (FJCC, 1987)

Load scheduling schemes using inter - PE network. - Kei Hiraki; Satoshi Sekiguchi; Toshio Shimada (Syst. Comput. Jpn., 1987)

Efficient vector processing on dataflow supercomputer SIGMA-1. - Kei Hiraki; Satoshi Sekiguchi; Toshio Shimada (SC, 1988)

Data flow language DFC: Design and implementation. - Toshio Shimada; Satoshi Sekiguchi; Kei Hiraki (Syst. Comput. Jpn., 1989)

Dataflow computer development in Japan. - Toshitsugu Yuba; Toshio Shimada; Yoshinori Yamaguchi; Kei Hiraki; Shuichi Sakai (ICS, 1990)

Sequential description and parallel execution language DFCII dataflow supercomputers. - Satoshi Sekiguchi; Toshio Shimada; Kei Hiraki (ICS, 1991)

Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism. - Kenji Toda; Kenji Nishida; Yoshinobu Uchibori; Shuichi Sakai; Toshio Shimada (IPPS, 1991)

A priority forwarding scheme for real-time multistage interconnection networks. - Kenji Toda; Kenji Nishida; Shuichi Sakai; Toshio Shimada (RTSS, 1992)

Real-Time Parallel Architecture for Sensor Funsion. - Toshio Shimada; Kenji Toda; Kenji Nishida (J. Parallel Distributed Comput., 1992)

Empirical Study of Latency Hiding on a Fine-Grain Parallel Processor. - Kei Hiraki; Toshio Shimada; Satoshi Sekiguchi (International Conference on Supercomputing, 1993)

The Hardware Architecture of the CODA Real-Time Parallel Processor. - Kenji Nishida; Kenji Toda; Toshio Shimada; Yoshinori Yamaguchi (PARCO, 1993)

An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. - Ryotaro Kobayashi; Yukihiro Ogawa; Hideki Ando; Toshio Shimada; Mitsuaki Iwata (EUROMICRO, 1999)

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. - Hajime Kubosawa; Naoshi Higaki; Satoshi Ando; Hiromasa Takahashi; Yoshimi Asada; Hideaki Anbutsu; Tomio Sato; Masato Sakate; Atsuhiro Suga; Michihide Kimura; Hideo Miyake; Hiroshi Okano; et al. (IEEE J. Solid State Circuits, 1999)

A preactivating mechanism for a VT-CMOS cache using address prediction. - Ryo Fujioka; Kiyokazu Katayama; Ryotaro Kobayashi; Hideki Ando; Toshio Shimada (ISLPED, 2002)

Pipeline stage unification: a low-energy consumption technique for future mobile processors. - Hajime Shimada; Hideki Ando; Toshio Shimada (ISLPED, 2003)

Limits of Thread-Level Parallelism in Non-numerical Programs. - Akio Nakajima; Ryotaro Kobayashi; Hideki Ando; Toshio Shimada (Inf. Media Technol., 2006)

Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation. - Akihiro Yamamoto; Yusuke Tanaka 001; Hideki Ando; Toshio Shimada (MEDEA@PACT, 2007)

Power consumption reduction scheme focusing on the Depth of Speculative Execution. - Hideki Oshima; Ryotaro Kobayashi; Kazuki Shimura; Toshio Shimada (CIT, 2008)

Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation. - Akihiro Yamamoto; Yusuke Tanaka 001; Hideki Ando; Toshio Shimada (Inf. Media Technol., 2008)