A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. - Takashi Sato 001; Yoji Nishio; Toshio Sugano; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1999)

Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps Operation. - Atsushi Hiraishi; Toshio Sugano; Hideki Kusamitsu (ASP-DAC, 2007)