A pulsed sensing scheme with a limited bit-line swing. - Roy E. Scheuerlein; Yasunao Katayama; Toshiaki Kirihata; Yoshinori Sakaue; Akashi Satoh; Toshio Sunaga; T. Yoshikawa; Koji Kitamura; Sang H. Dhong (IEEE J. Solid State Circuits, 1992)

A 14-ns 14-Mb CMOS DRAM with 300-mW active power. - Toshiaki Kirihata; Sang H. Dhong; Koji Kitamura; Toshio Sunaga; Yasunao Katayama; Roy E. Scheuerlein; Akashi Satoh; Yoshinori Sakaue; Kentaroh Tobimatsu; Koji Hosokawa; Takaki Saitoh; Takefumi Yoshikawa; et al. (IEEE J. Solid State Circuits, 1992)

A 30-ns cycle time 4-Mb mask ROM. - Toshio Sunaga (IEEE J. Solid State Circuits, 1994)

Combined DRAM and logic chip for massively parallel systems. - Peter M. Kogge; Toshio Sunaga; Hisatada Miyataka; Koji Kitamura; Eric Retter (ARVLSI, 1995)

A 64Kb - 32 DRAM for graphics applications. - Toshio Sunaga; Koji Hosokawa; Sang H. Dhong; Koji Kitamura (IBM J. Res. Dev., 1995)

A variable precharge voltage sensing. - Toshiaki Eirihata; Sang H. Dhong; Lewis M. Terman; Toshio Sunaga; Yoischi Taira (IEEE J. Solid State Circuits, 1995)

A full bit prefetch DRAM sensing circuit. - Toshio Sunaga (IEEE J. Solid State Circuits, 1996)

A parallel processing chip with embedded DRAM macros. - Toshio Sunaga; Hisatada Miyatake; Koji Kitamura; Peter M. Kogge; Eric Retter (IEEE J. Solid State Circuits, 1996)

An eight-bit prefetch circuit for high-bandwidth DRAM's. - Toshio Sunaga; Koji Hosokawa; Yutaka Nakamura; Manabu Ichinose; Yasuyuki Igarashi (IEEE J. Solid State Circuits, 1997)