Voltage limiters for DRAMs with substrate-plate-electrode memory cells. - Toshio Takeshima; Masahide Takada; Toshiyuki Shimizu; Takuya Katoh; Mitsuru Sakamoto (IEEE J. Solid State Circuits, 1988)

A BIST scheme using microprogram ROM for large capacity memories. - Hiroki Koike; Toshio Takeshima; Masahide Takada (ITC, 1990)

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. - Toshio Takeshima; Masahide Takada; Hiroki Koike; Hiroshi Watanabe; Shigeru Koshimaru; Kenjiro Mitake; Wataru Kikuchi; Takaho Tanigawa; Tatsunori Murotani; Kenji Noda; Kazuhiro Tasaka; Koji Yamanaka; et al. (IEEE J. Solid State Circuits, 1990)

A 5-ns 1-Mb ECL BiCMOS SRAM. - Masahide Takada; Kazuyuki Nakamura; Toshio Takeshima; Koichiro Furuta; Tohru Yamazaki; Kiyotaka Imai; Susumu Ohi; Yumi Sekine; Yukio Minato; Hisamitsu Kimuto (IEEE J. Solid State Circuits, 1990)

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell. - Masayoshi Ohkawa; Hiroshi Sugawara; Naoaki Sudo; Masaru Tsukiji; Ken-ichiro Nakagawa; Masato Kawata; Ken-ichi Oyama; Toshio Takeshima; Shuichi Ohya (IEEE J. Solid State Circuits, 1996)