A 4-Mbit DRAM with 16-bit concurrent ECC. - Toshio Yamada; Hisakazu Kotani; Junko Matsushima; Michihiro Inoue (IEEE J. Solid State Circuits, 1988)

A 64-Mb DRAM with meshed power line. - Toshio Yamada; Yoshiro Nakata; Junko Hasegawa; Noriaki Amano; Akinori Shibayama; Masaru Sasago; Naoto Matsuo; Toshiki Yabu; Susumu Matsumoto; Shozo Okada; Michihiro Inoue (IEEE J. Solid State Circuits, 1991)

A New Testing Acceleration Chip for Low-Cost Memory Tests. - Michihiro Inoue; Toshio Yamada; Atsushi Fujiwara (IEEE Des. Test Comput., 1993)

CABINet: networking of immersive projection environment. - Tetsuro Ogi; Toshio Yamada; Michitaka Hirose (HCI (2), 1999)

Development of Stereo Video Avatar in Networked Immersive Projection Environment. - Michitaka Hirose; Tetsuro Ogi; Toshio Yamada; Ken Tamagawa (ICIP (3), 1999)

Integrating Live Video for Immersive Environments. - Michitaka Hirose; Tetsuro Ogi; Toshio Yamada (IEEE Multim., 1999)

Development and evaluation of the CABIN immersive multiscreen display. - Michitaka Hirose; Tetsuro Ogi; Shohei Ishiwata; Toshio Yamada (Syst. Comput. Jpn., 1999)

An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D2/RAM). - Yasuhiro Agata; Kenji Motomochi; Yoshifumi Fukushima; Masanori Shirahama; Marefusa Kurumada; Naoki Kuroda; Hiroyuki Sadakata; Kohtaro Hayashi; Toshio Yamada; Kazunari Takahashi; Tsutomu Fujita (IEEE J. Solid State Circuits, 2000)

Invisible Interface for the Immersive Virtual World. - Tetsuro Ogi; Toshio Yamada; Koji Yamamoto; Michitaka Hirose (EGVE/IPT, 2001)

Multimedia Virtual Laboratory. - Tetsuro Ogi; Toshio Yamada; Koichi Hirota; Michitaka Hirose (INTERACT, 2001)

Experience of Immersive Virtual World Using Cellular Phone Interface. - Tetsuro Ogi; Koji Yamamoto; Toshio Yamada; Michitaka Hirose (IEEE Pacific Rim Conference on Multimedia, 2001)

Immersive Telecommunication Using Stereo Video Avatar. - Tetsuro Ogi; Toshio Yamada; Ken Tamagawa; Makoto Kano; Michitaka Hirose (VR, 2001)

Developing a 2.5-D video avatar. - Ken Tamagawa; Toshio Yamada; Tetsuro Ogi; Michitaka Hirose (IEEE Signal Process. Mag., 2001)

Desk-Sized Immersive Workplace Using Force Feedback Grid Interface. - Toshio Yamada; Daisuke Tsubouchi; Tetsuro Ogi; Michitaka Hirose (VR, 2002)

High Presence Remote Presentation in the Shared Immersive Virtual World. - Tetsuro Ogi; Toshio Yamada; Michitaka Hirose; Masahiro Fujita; Kazuto Kuzuu (VR, 2003)

MVL Toolkit: Software Library for Constructing an Immersive Shared Virtual World. - Tetsuro Ogi; Takuro Kayahara; Toshio Yamada; Michitaka Hirose (VR, 2004)

Accurate analysis of substrate sensitivity of active transistors in an analog circuit. - Satoshi Takaya; Yoji Bando; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (ISQED, 2011)

A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. - Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2011)

On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. - Masaaki Souda; Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2011)

On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors. - Yoji Bando; Satoshi Takaya; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2012)

Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. - Satoshi Takaya; Yoji Bando; Toru Ohkawa; Toshiharu Takaramoto; Toshio Yamada; Masaaki Souda; Shigetaka Kumashiro; Tohru Mogami; Makoto Nagata (IEICE Trans. Electron., 2013)