A CMOS gate array with dynamic-termination GTL I/O circuits. - Junya Kudoh; Toshiro Takahashi; Yukio Umada; Masaharu Kimura; Shigeru Yamamoto; Youichi Ito (ICCD, 1995)

A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits. - Toshiro Takahashi; Makio Uchida; Takahiko Takahashi; Ryozo Yoshino; Masakazu Yamamoto; Nobuh Kitamura (IEEE J. Solid State Circuits, 1995)

110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock. - Toshiro Takahashi; Takashi Muto; Yuji Shirai; Fumihiko Shirotori; Yoshifumi Takada; Akira Yamagiwa; Akira Nishida; Atsuo Hotta; Tadashi Kiyuna (IEEE J. Solid State Circuits, 1999)

Simultaneous bidirectional transceiver logic. - Kenichi Ishibashi; Tsutomu Goto; Takehisa Hayashi; Tetsuhiko Okada; Akira Yamagiwa; Masabumi Shibata; Kazuhiro Akimoto; Naoki Hamanaka; Toshiro Takahashi; Akio Koyama; Tatsuhiro Aida (IEEE Micro, 1999)