A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array. - Katsuyuki Sato; Mitsuteru Kobayashi; Hiroyuki Hida; Hideyuki Miyazawa; Yuji Shirai; Kenji Fujita; Toshiyuki Nakao; Masamichi Ishihara (IEEE J. Solid State Circuits, 1992)

Generating Dual-Directed Recommendation Information from Point-of-Sales Data of a Supermarket. - Masakazu Takahashi; Toshiyuki Nakao; Kazuhiko Tsuda; Takao Terano (KES (2), 2008)