An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. - Katsuhiro Suma; Takahiro Tsuruda; Hideto Hidaka; Takahisa Eimori; Toshiyuki Oashi; Yasuo Yamaguchi; Toshiaki Iwamatsu; Masakazu Hirose; Fukashi Morishita; Kazutarni Arimoto; Kazuyasu Fujishima; Yasuo Inoue; et al. (IEEE J. Solid State Circuits, 1994)

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. - Ken'ichi Shimomura; Hiroki Shimano; Narumi Sakashita; Fumihiro Okuda; Toshiyuki Oashi; Yasuo Yamaguchi; Takahisa Eimori; Masahide Inuishi; Kazutami Arimoto; Shigeto Maegawa; Yasuo Inoue; Shinji Komori; et al. (IEEE J. Solid State Circuits, 1997)

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. - Makoto Yabuuchi; Koji Nii; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (ISSCC, 2007)

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. - Satoshi Ishikura; Marefusa Kurumada; Toshio Terano; Yoshinobu Yamagami; Naoki Kotani; Katsuji Satomi; Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Toshiyuki Oashi; Hiroshi Makino; et al. (IEEE J. Solid State Circuits, 2008)

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. - Koji Nii; Makoto Yabuuchi; Yasumasa Tsukamoto; Shigeki Ohbayashi; Susumu Imaoka; Hiroshi Makino; Yoshinobu Yamagami; Satoshi Ishikura; Toshio Terano; Toshiyuki Oashi; Keiji Hashimoto; Akio Sebe; et al. (IEEE J. Solid State Circuits, 2008)